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infrastructure to change SW without re-synthesizing
Stefan Schuermans authored on 2012-03-25 02:16:26
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implementation of ethernet and ARP (not completely working yet, hangs on received ARP request)
Stefan Schuermans authored on 2012-03-17 01:03:19
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made MAC configurable in ethernet peripheral
Stefan Schuermans authored on 2012-03-11 20:48:30
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fixed uninitialized / not resetted frame done output of ethernet TX frame processing
Stefan Schuermans authored on 2012-03-10 10:56:08
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implemented ethernet RX packet and TX clock in testbed
Stefan Schuermans authored on 2012-03-06 20:48:33
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implemented ethernet TX interface (not tested yet)
Stefan Schuermans authored on 2012-03-04 21:38:35
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implemented ethernet RX busmaster -> packet reception working
Stefan Schuermans authored on 2012-03-03 23:42:55
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changed MIPS core to use read and write ack instead of stall input
Stefan Schuermans authored on 2012-02-29 21:28:37
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removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy
Stefan Schuermans authored on 2012-02-21 20:40:30
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begin of ethernet RX implementation, so far only test interface to core, does not meet timing
Stefan Schuermans authored on 2012-02-20 21:16:03
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implemented loading of data memory from firmware
Stefan Schuermans authored on 2012-02-12 17:47:50
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clock and reset constraints are for whole system
Stefan Schuermans authored on 2012-02-10 23:22:30
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implented basic system with core, instr memory, data memory
Stefan Schuermans authored on 2012-02-06 21:28:00
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second version of multiplier (slower, i.e. more stages -> faster clock)
Stefan Schuermans authored on 2012-02-05 21:39:45
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start of MIPS core: begin of decoder and ALU
Stefan Schuermans authored on 2012-01-23 22:06:18