mips_sys

fixed uninitialized / not resetted frame done output of ethernet TX frame processing
Parent 1f34390
Stefan Schuermans

Stefan Schuermans commited on 2012-03-10 10:56:08
Showing 3 changed files, with 83 additions and 33 deletions.

Default.wcfg
View file @ 13632e3
... ... 
@@ -15,7 +15,7 @@
15 15 
          </top_modules>
16 16 
       </db_ref>
17 17 
    </db_ref_list>
18 
-   <WVObjectSize size="18" />
18 
+   <WVObjectSize size="29" />
19 19 
    <wvobject fp_name="/e_testbed/s_clk" type="logic" db_ref_id="1">
20 20 
       <obj_property name="ElementShortName">s_clk</obj_property>
21 21 
       <obj_property name="ObjectShortName">s_clk</obj_property>
... ... 
@@ -93,4 +93,53 @@
93 93 
       <obj_property name="ElementShortName">o_bm_rd_en[3:0]</obj_property>
94 94 
       <obj_property name="ObjectShortName">o_bm_rd_en[3:0]</obj_property>
95 95 
    </wvobject>
96 
+   <wvobject fp_name="/e_testbed/system/eth/txif/i_data" type="array" db_ref_id="1">
97 
+      <obj_property name="ElementShortName">i_data[7:0]</obj_property>
98 
+      <obj_property name="ObjectShortName">i_data[7:0]</obj_property>
99 
+      <obj_property name="Radix">HEXRADIX</obj_property>
100 
+   </wvobject>
101 
+   <wvobject fp_name="/e_testbed/system/eth/txif/o_data_ack" type="logic" db_ref_id="1">
102 
+      <obj_property name="ElementShortName">o_data_ack</obj_property>
103 
+      <obj_property name="ObjectShortName">o_data_ack</obj_property>
104 
+   </wvobject>
105 
+   <wvobject fp_name="/e_testbed/system/eth/txif/i_data_en" type="logic" db_ref_id="1">
106 
+      <obj_property name="ElementShortName">i_data_en</obj_property>
107 
+      <obj_property name="ObjectShortName">i_data_en</obj_property>
108 
+   </wvobject>
109 
+   <wvobject fp_name="/e_testbed/system/eth/txframe/i_frame_en" type="logic" db_ref_id="1">
110 
+      <obj_property name="ElementShortName">i_frame_en</obj_property>
111 
+      <obj_property name="ObjectShortName">i_frame_en</obj_property>
112 
+   </wvobject>
113 
+   <wvobject fp_name="/e_testbed/system/eth/txframe/i_frame_data" type="array" db_ref_id="1">
114 
+      <obj_property name="ElementShortName">i_frame_data[31:0]</obj_property>
115 
+      <obj_property name="ObjectShortName">i_frame_data[31:0]</obj_property>
116 
+      <obj_property name="Radix">HEXRADIX</obj_property>
117 
+   </wvobject>
118 
+   <wvobject fp_name="/e_testbed/system/eth/txframe/i_frame_data_en" type="logic" db_ref_id="1">
119 
+      <obj_property name="ElementShortName">i_frame_data_en</obj_property>
120 
+      <obj_property name="ObjectShortName">i_frame_data_en</obj_property>
121 
+   </wvobject>
122 
+   <wvobject fp_name="/e_testbed/system/eth/txframe/o_frame_data_ack" type="logic" db_ref_id="1">
123 
+      <obj_property name="ElementShortName">o_frame_data_ack</obj_property>
124 
+      <obj_property name="ObjectShortName">o_frame_data_ack</obj_property>
125 
+   </wvobject>
126 
+   <wvobject fp_name="/e_testbed/system/eth/txframe/o_frame_done" type="logic" db_ref_id="1">
127 
+      <obj_property name="ElementShortName">o_frame_done</obj_property>
128 
+      <obj_property name="ObjectShortName">o_frame_done</obj_property>
129 
+   </wvobject>
130 
+   <wvobject fp_name="/e_testbed/system/eth/r_tx_start" type="array" db_ref_id="1">
131 
+      <obj_property name="ElementShortName">r_tx_start[31:0]</obj_property>
132 
+      <obj_property name="ObjectShortName">r_tx_start[31:0]</obj_property>
133 
+      <obj_property name="Radix">HEXRADIX</obj_property>
134 
+   </wvobject>
135 
+   <wvobject fp_name="/e_testbed/system/eth/r_tx_end" type="array" db_ref_id="1">
136 
+      <obj_property name="ElementShortName">r_tx_end[31:0]</obj_property>
137 
+      <obj_property name="ObjectShortName">r_tx_end[31:0]</obj_property>
138 
+      <obj_property name="Radix">HEXRADIX</obj_property>
139 
+   </wvobject>
140 
+   <wvobject fp_name="/e_testbed/system/eth/r_tx_pos" type="array" db_ref_id="1">
141 
+      <obj_property name="ElementShortName">r_tx_pos[31:0]</obj_property>
142 
+      <obj_property name="ObjectShortName">r_tx_pos[31:0]</obj_property>
143 
+      <obj_property name="Radix">HEXRADIX</obj_property>
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+   </wvobject>
96 145 
 </wave_config>
io/eth/txframe.vhd
View file @ 13632e3
... ... 
@@ -73,6 +73,7 @@ BEGIN
73 73 
         o_if_data        <= X"00";
74 74 
         o_if_data_en     <= '0';
75 75 
         o_frame_data_ack <= '0';
76 
+        o_frame_done     <= '0';
76 77 
         s_crc_en         <= '0';
77 78 
         s_crc_start      <= '0';
78 79 
         s_crc_data       <= (OTHERS => '0');
mips_sys.xise
View file @ 13632e3
... ... 
@@ -17,7 +17,7 @@
17 17 
   <files>
18 18 
     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19 19 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
20 
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
20 
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
21 21 
     </file>
22 22 
     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
23 23 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
... ... 
@@ -25,35 +25,35 @@
25 25 
     </file>
26 26 
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27 27 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
28 
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
28 
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
29 29 
     </file>
30 30 
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31 31 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
32 
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
33 33 
     </file>
34 34 
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35 35 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
36 
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
37 37 
     </file>
38 38 
     <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
39 39 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
40 
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
41 41 
     </file>
42 42 
     <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
43 43 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
44 
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
44 
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
45 45 
     </file>
46 46 
     <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
47 47 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
48 
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
48 
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
49 49 
     </file>
50 50 
     <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
51 51 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
52 
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
52 
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
53 53 
     </file>
54 54 
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55 55 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
57 57 
     </file>
58 58 
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59 59 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
... ... 
@@ -63,11 +63,11 @@
63 63 
     </file>
64 64 
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65 65 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
67 67 
     </file>
68 68 
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69 69 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
70 
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
71 71 
     </file>
72 72 
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
73 73 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
... ... 
@@ -77,99 +77,99 @@
77 77 
     </file>
78 78 
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
79 79 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
80 
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
81 81 
     </file>
82 82 
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
83 83 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
84 
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
85 85 
     </file>
86 86 
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
87 87 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
88 
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
88 
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
89 89 
     </file>
90 90 
     <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
91 91 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
92 92 
     </file>
93 93 
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
94 94 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
95 
-      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
95 
+      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
96 96 
     </file>
97 97 
     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
98 98 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
100 100 
     </file>
101 101 
     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
102 102 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
103 
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
104 104 
     </file>
105 105 
     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
106 106 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
107 
-      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
108 108 
     </file>
109 109 
     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
110 110 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
112 112 
     </file>
113 113 
     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
114 114 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
116 116 
     </file>
117 117 
     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118 118 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119 119 
     </file>
120 120 
     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
121 121 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
122 
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
123 123 
     </file>
124 124 
     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
125 125 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
126 126 
     </file>
127 127 
     <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
128 128 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
129 
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
129 
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
130 130 
     </file>
131 131 
     <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
132 132 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
133 
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
133 
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
134 134 
     </file>
135 135 
     <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
136 136 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
137 
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
137 
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
138 138 
     </file>
139 139 
     <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
140 140 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
141 
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
141 
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
142 142 
     </file>
143 143 
     <file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
144 144 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
145 
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
145 
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
146 146 
     </file>
147 147 
     <file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
148 148 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
149 149 
     </file>
150 150 
     <file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL">
151 151 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
152 
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
152 
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
153 153 
     </file>
154 154 
     <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
155 155 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
156 
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
156 
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
157 157 
     </file>
158 158 
     <file xil_pn:name="io/eth/txif.vhd" xil_pn:type="FILE_VHDL">
159 159 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
160 
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
160 
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
161 161 
     </file>
162 162 
     <file xil_pn:name="io/eth/txframe.vhd" xil_pn:type="FILE_VHDL">
163 163 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
164 
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
164 
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
165 165 
     </file>
166 166 
     <file xil_pn:name="blocks/rwram_dc.vhd" xil_pn:type="FILE_VHDL">
167 167 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
168 
-      <association xil_pn:name="Implementation" xil_pn:seqID="214"/>
168 
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
169 169 
     </file>
170 170 
     <file xil_pn:name="blocks/fifo_dc.vhd" xil_pn:type="FILE_VHDL">
171 171 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
172 
-      <association xil_pn:name="Implementation" xil_pn:seqID="215"/>
172 
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
173 173 
     </file>
174 174 
   </files>
175 175
176 176