removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy
Stefan Schuermans commited on 2012-02-21 20:40:30
Showing 2 changed files, with 39 additions and 11 deletions.
- mips_sys.xise 065c1e1..5897883
- system/system.vhd 1c3dba4..70a16ed
| ... | ... |
@@ -269,7 +269,7 @@ |
| 269 | 269 |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
| 270 | 270 |
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
| 271 | 271 |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
| 272 |
- <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
|
| 272 |
+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/> |
|
| 273 | 273 |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
| 274 | 274 |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
| 275 | 275 |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
| ... | ... |
@@ -37,6 +37,9 @@ ARCHITECTURE a_system OF e_system IS |
| 37 | 37 |
SIGNAL s_dbus_rd_data: std_logic_vector(31 DOWNTO 0); |
| 38 | 38 |
SIGNAL s_dbus_wr_data: std_logic_vector(31 DOWNTO 0); |
| 39 | 39 |
SIGNAL s_dbus_wr_en: std_logic_vector( 3 DOWNTO 0); |
| 40 |
+ |
|
| 41 |
+ SIGNAL r_dbus_addr_delay: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0'); |
|
| 42 |
+ |
|
| 40 | 43 |
SIGNAL s_data_addr: std_logic_vector(31 DOWNTO 0); |
| 41 | 44 |
SIGNAL s_data_rd_data: std_logic_vector(31 DOWNTO 0); |
| 42 | 45 |
SIGNAL s_data_wr_data: std_logic_vector(31 DOWNTO 0); |
| ... | ... |
@@ -238,7 +241,16 @@ BEGIN |
| 238 | 241 |
o_data => s_instr_data |
| 239 | 242 |
); |
| 240 | 243 |
|
| 241 |
- p_dbus: PROCESS(s_dbus_addr, s_dbus_wr_data, s_dbus_wr_en, |
|
| 244 |
+ p_dbus_rd_sync: PROCESS(rst, clk) |
|
| 245 |
+ BEGIN |
|
| 246 |
+ IF rst = '1' THEN |
|
| 247 |
+ r_dbus_addr_delay <= (OTHERS => '0'); |
|
| 248 |
+ ELSIF rising_edge(clk) THEN |
|
| 249 |
+ r_dbus_addr_delay <= s_dbus_addr; |
|
| 250 |
+ END IF; |
|
| 251 |
+ END PROCESS p_dbus_rd_sync; |
|
| 252 |
+ |
|
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+ p_dbus_rd: PROCESS(r_dbus_addr_delay, |
|
| 242 | 254 |
s_data_rd_data, |
| 243 | 255 |
s_leds_rd_data, |
| 244 | 256 |
s_lcd_rd_data, |
| ... | ... |
@@ -246,11 +258,34 @@ BEGIN |
| 246 | 258 |
s_uart_rd_data, |
| 247 | 259 |
s_eth_rd_data, |
| 248 | 260 |
s_cyc_cnt_rd_data) |
| 261 |
+ BEGIN |
|
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+ s_dbus_rd_data <= (OTHERS => '0'); |
|
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+ IF r_dbus_addr_delay(31) = '0' THEN |
|
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+ s_dbus_rd_data <= s_data_rd_data; |
|
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+ ELSIF r_dbus_addr_delay(31 DOWNTO 16) = X"8000" THEN |
|
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+ CASE r_dbus_addr_delay(15 DOWNTO 8) IS |
|
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+ WHEN X"00" => |
|
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+ s_dbus_rd_data <= X"000000" & s_leds_rd_data; |
|
| 269 |
+ WHEN X"01" => |
|
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+ s_dbus_rd_data <= s_lcd_rd_data; |
|
| 271 |
+ WHEN X"02" => |
|
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+ s_dbus_rd_data <= s_switches_rd_data; |
|
| 273 |
+ WHEN X"03" => |
|
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+ s_dbus_rd_data <= s_uart_rd_data; |
|
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+ WHEN X"04" => |
|
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+ s_dbus_rd_data <= s_eth_rd_data; |
|
| 277 |
+ WHEN X"10" => |
|
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+ s_dbus_rd_data <= s_cyc_cnt_rd_data; |
|
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+ WHEN OTHERS => NULL; |
|
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+ END CASE; |
|
| 281 |
+ END IF; |
|
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+ END PROCESS p_dbus_rd; |
|
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+ |
|
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+ p_dbus_wr: PROCESS(s_dbus_addr, s_dbus_wr_data, s_dbus_wr_en) |
|
| 249 | 285 |
VARIABLE v_wr_en_word: std_logic; |
| 250 | 286 |
BEGIN |
| 251 | 287 |
v_wr_en_word := s_dbus_wr_en(0) AND s_dbus_wr_en(1) AND |
| 252 | 288 |
s_dbus_wr_en(2) AND s_dbus_wr_en(3); |
| 253 |
- s_dbus_rd_data <= (OTHERS => '0'); |
|
| 254 | 289 |
s_data_addr <= (OTHERS => '0'); |
| 255 | 290 |
s_data_wr_data <= (OTHERS => '0'); |
| 256 | 291 |
s_data_wr_en <= (OTHERS => '0'); |
| ... | ... |
@@ -268,41 +303,34 @@ BEGIN |
| 268 | 303 |
s_cyc_cnt_wr_data <= (OTHERS => '0'); |
| 269 | 304 |
s_cyc_cnt_wr_en <= '0'; |
| 270 | 305 |
IF s_dbus_addr(31) = '0' THEN |
| 271 |
- s_dbus_rd_data <= s_data_rd_data; |
|
| 272 | 306 |
s_data_addr <= s_dbus_addr; |
| 273 | 307 |
s_data_wr_data <= s_dbus_wr_data; |
| 274 | 308 |
s_data_wr_en <= s_dbus_wr_en; |
| 275 | 309 |
ELSIF s_dbus_addr(31 DOWNTO 16) = X"8000" THEN |
| 276 | 310 |
CASE s_dbus_addr(15 DOWNTO 8) IS |
| 277 | 311 |
WHEN X"00" => |
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- s_dbus_rd_data <= X"000000" & s_leds_rd_data; |
|
| 279 | 312 |
s_leds_wr_data <= s_dbus_wr_data(7 DOWNTO 0); |
| 280 | 313 |
s_leds_wr_en <= s_dbus_wr_en(0); |
| 281 | 314 |
WHEN X"01" => |
| 282 |
- s_dbus_rd_data <= s_lcd_rd_data; |
|
| 283 | 315 |
s_lcd_wr_data <= s_dbus_wr_data; |
| 284 | 316 |
s_lcd_wr_en <= s_dbus_wr_en; |
| 285 | 317 |
WHEN X"02" => |
| 286 |
- s_dbus_rd_data <= s_switches_rd_data; |
|
| 287 | 318 |
s_switches_addr <= s_dbus_addr(2 DOWNTO 0); |
| 288 | 319 |
WHEN X"03" => |
| 289 |
- s_dbus_rd_data <= s_uart_rd_data; |
|
| 290 | 320 |
s_uart_addr <= s_dbus_addr(3 DOWNTO 0); |
| 291 | 321 |
s_uart_wr_data <= s_dbus_wr_data; |
| 292 | 322 |
s_uart_wr_en <= s_dbus_wr_en; |
| 293 | 323 |
WHEN X"04" => |
| 294 |
- s_dbus_rd_data <= s_eth_rd_data; |
|
| 295 | 324 |
s_eth_addr <= s_dbus_addr(3 DOWNTO 0); |
| 296 | 325 |
s_eth_wr_data <= s_dbus_wr_data; |
| 297 | 326 |
s_eth_wr_en <= s_dbus_wr_en; |
| 298 | 327 |
WHEN X"10" => |
| 299 |
- s_dbus_rd_data <= s_cyc_cnt_rd_data; |
|
| 300 | 328 |
s_cyc_cnt_wr_data <= s_dbus_wr_data; |
| 301 | 329 |
s_cyc_cnt_wr_en <= v_wr_en_word; |
| 302 | 330 |
WHEN OTHERS => NULL; |
| 303 | 331 |
END CASE; |
| 304 | 332 |
END IF; |
| 305 |
- END PROCESS p_dbus; |
|
| 333 |
+ END PROCESS p_dbus_wr; |
|
| 306 | 334 |
|
| 307 | 335 |
data_0: e_ram_0 |
| 308 | 336 |
GENERIC MAP ( |
| 309 | 337 |