mips_sys

separated shifter from ALU
Parent 8072c84
Stefan Schuermans

Stefan Schuermans commited on 2012-01-24 20:43:21
Showing 5 changed files, with 124 additions and 31 deletions.

mips/alu.vhd
View file @ 0a29d2e
... ... 
@@ -14,52 +14,58 @@ END ENTITY e_mips_alu;
14 14
15 15 
 ARCHITECTURE a_mips_alu OF e_mips_alu IS
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+    SIGNAL s_shift_arith: std_logic;
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+    SIGNAL s_shift_left:  std_logic;
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+    SIGNAL s_shift_out:   std_logic_vector(31 DOWNTO 0);
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+
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+    COMPONENT e_mips_shifter IS
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+        PORT (
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+            i_arith: IN  std_logic;
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+            i_left:  IN  std_logic;
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+            i_val:   IN  std_logic_vector(31 DOWNTO 0);
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+            i_num:   IN  std_logic_vector(31 DOWNTO 0);
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+            o_val:   OUT std_logic_vector(31 DOWNTO 0)
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+        );
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+    END COMPONENT e_mips_shifter;
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+
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 BEGIN
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-    p_alu: PROCESS(i_alu, i_op1, i_op2)
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+    shifter: e_mips_shifter
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+        PORT MAP (
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+            i_arith => s_shift_arith,
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+            i_left  => s_shift_left,
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+            i_val   => i_op1,
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+            i_num   => i_op2,
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+            o_val   => s_shift_out
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+        );
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+
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+    p_alu: PROCESS(i_alu, i_op1, i_op2, s_shift_out)
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         VARIABLE v_op1_s: signed(31 DOWNTO 0);
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         VARIABLE v_op2_s: signed(31 DOWNTO 0);
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         VARIABLE v_op1_u: unsigned(31 DOWNTO 0);
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         VARIABLE v_op2_u: unsigned(31 DOWNTO 0);
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-        VARIABLE v_int5:  integer RANGE 31 DOWNTO 0;
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-        VARIABLE v_tmp64: std_logic_vector(63 DOWNTO 0);
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     BEGIN
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         v_op1_s := signed(i_op1);
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         v_op2_s := signed(i_op2);
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         v_op1_u := unsigned(i_op1);
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         v_op2_u := unsigned(i_op2);
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+        s_shift_arith <= '0';
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+        s_shift_left <= '0';
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         CASE i_alu IS
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             WHEN alu_add => o_res <= std_logic_vector(v_op1_s + v_op2_s);
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             WHEN alu_and => o_res <= i_op1 AND i_op2;
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             WHEN alu_nor => o_res <= i_op1 NOR i_op2;
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             WHEN alu_or  => o_res <= i_op1 OR i_op2;
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             WHEN alu_sub => o_res <= std_logic_vector(v_op1_s - v_op2_s);
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-            WHEN alu_sll => IF i_op2(31 DOWNTO 5) = X"000000" & "000" THEN
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-                                v_int5  := to_integer(v_op2_u(4 DOWNTO 0));
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-                                v_tmp64 := i_op1 & X"00000000";
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-                                o_res   <= v_tmp64(v_int5 + 31 DOWNTO v_int5);
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-                            ELSE
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-                                o_res   <= X"00000000";
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-                            END IF;
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-            WHEN alu_sra => IF i_op2(31 DOWNTO 5) = X"000000" & "000" THEN
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-                                v_int5  := to_integer(v_op2_u(4 DOWNTO 0));
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-                                IF i_op1(31) = '1' THEN
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-                                    v_tmp64 := X"FFFFFFFF" & i_op1;
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-                                ELSE
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-                                    v_tmp64 := X"00000000" & i_op1;
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-                                END IF;
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-                                o_res   <= v_tmp64(63 - v_int5 DOWNTO 32 - v_int5);
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-                            ELSE
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-                                o_res   <= X"00000000";
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-                            END IF;
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-            WHEN alu_srl => IF i_op2(31 DOWNTO 5) = X"000000" & "000" THEN
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-                                v_int5  := to_integer(v_op2_u(4 DOWNTO 0));
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-                                v_tmp64 := X"00000000" & i_op1;
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-                                o_res   <= v_tmp64(63 - v_int5 DOWNTO 32 - v_int5);
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+            WHEN alu_sll => s_shift_arith <= '0'; s_shift_left <= '1'; o_res <= s_shift_out;
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+            WHEN alu_sra => s_shift_arith <= '1'; s_shift_left <= '0'; o_res <= s_shift_out;
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+            WHEN alu_srl => s_shift_arith <= '1'; s_shift_left <= '0'; o_res <= s_shift_out;
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+            WHEN alu_slt => IF v_op1_s < v_op2_s THEN
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+                                o_res <= X"00000001";
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                             ELSE
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                                 o_res <= X"00000000";
61 67 
                             END IF;
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-            WHEN alu_slt => IF v_op1_s < v_op2_s THEN
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+            WHEN alu_sltu => IF v_op1_u < v_op2_u THEN
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                                  o_res <= X"00000001";
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                              ELSE
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                                  o_res <= X"00000000";
mips/decoder.vhd
View file @ 0a29d2e
... ... 
@@ -128,7 +128,7 @@ BEGIN
128 128 
                     WHEN "100110" => o_op <= op_alu; o_alu <= alu_xor;
129 129 
                     WHEN "100111" => o_op <= op_alu; o_alu <= alu_nor;
130 130 
                     WHEN "101010" => o_op <= op_alu; o_alu <= alu_slt;
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-                    WHEN "101011" => o_op <= op_alu; o_alu <= alu_slt;
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+                    WHEN "101011" => o_op <= op_alu; o_alu <= alu_sltu;
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                     WHEN OTHERS => NULL;
133 133 
                 END CASE;
134 134 
             WHEN "000010" => o_op <= op_j;
... ... 
@@ -140,7 +140,7 @@ BEGIN
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             WHEN "001000" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
141 141 
             WHEN "001001" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
142 142 
             WHEN "001010" => o_op <= op_alu; o_alu <= alu_slt; o_imm <= imm_16se;
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-            WHEN "001011" => o_op <= op_alu; o_alu <= alu_slt; o_imm <= imm_16se;
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+            WHEN "001011" => o_op <= op_alu; o_alu <= alu_sltu; o_imm <= imm_16se;
144 144 
             WHEN "001100" => o_op <= op_alu; o_alu <= alu_and; o_imm <= imm_16ze;
145 145 
             WHEN "001101" => o_op <= op_alu; o_alu <= alu_or; o_imm <= imm_16ze;
146 146 
             WHEN "001110" => o_op <= op_alu; o_alu <= alu_xor; o_imm <= imm_16ze;
mips/shifter.vhd
View file @ 0a29d2e
... ... 
@@ -0,0 +1,82 @@
1 
+LIBRARY ieee;
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+USE ieee.std_logic_1164.all;
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+USE ieee.numeric_std.all;
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+USE work.mips_types.all;
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+
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+ENTITY e_mips_shifter IS
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+    PORT (
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+        i_arith: IN  std_logic;
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+        i_left:  IN  std_logic;
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+        i_val:   IN  std_logic_vector(31 DOWNTO 0);
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+        i_num:   IN  std_logic_vector(31 DOWNTO 0);
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+        o_val:   OUT std_logic_vector(31 DOWNTO 0)
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+    );
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+END ENTITY e_mips_shifter;
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+
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+ARCHITECTURE a_mips_shifter OF e_mips_shifter IS
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+
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+    SIGNAL s_in:   std_logic_vector(31 DOWNTO 0);
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+    SIGNAL s_fill: std_logic;
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+    SIGNAL s_out:  std_logic_vector(31 DOWNTO 0);
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+
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+    FUNCTION l_shift(b:    std_logic;
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+                     val:  std_logic_vector(31 DOWNTO 0);
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+                     n:    natural) RETURN std_logic_vector IS
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+        VARIABLE v_fill: std_logic_vector(31 DOWNTO 0);
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+    BEGIN
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+        v_fill := (OTHERS => '0');
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+        IF b = '1' THEN
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+            RETURN val(31 - n DOWNTO 0) & v_fill(n - 1 DOWNTO 0);
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+        ELSE
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+            RETURN val;
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+        END IF;
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+    END FUNCTION l_shift;
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+
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+    FUNCTION r_shift(b:    std_logic;
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+                     val:  std_logic_vector(31 DOWNTO 0);
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+                     fill: std_logic;
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+                     n:    natural) RETURN std_logic_vector IS
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+        VARIABLE v_fill: std_logic_vector(31 DOWNTO 0);
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+    BEGIN
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+        v_fill := (OTHERS => fill);
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+        IF b = '1' THEN
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+            RETURN v_fill(n - 1 DOWNTO 0) & val(31 DOWNTO n);
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+        ELSE
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+            RETURN val;
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+        END IF;
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+    END FUNCTION r_shift;
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+
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+BEGIN
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+
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+    s_fill <= i_arith AND s_in(31);
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+
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+    p_shift: PROCESS(i_val, i_num)
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+        VARIABLE v1:   std_logic_vector(31 DOWNTO 0);
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+        VARIABLE v2:   std_logic_vector(31 DOWNTO 0);
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+        VARIABLE v3:   std_logic_vector(31 DOWNTO 0);
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+        VARIABLE v4:   std_logic_vector(31 DOWNTO 0);
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+        VARIABLE v5:   std_logic_vector(31 DOWNTO 0);
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+        CONSTANT zero: std_logic_vector(31 DOWNTO 5) := (OTHERS => '0');
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+    BEGIN
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+        IF i_left = '1' THEN
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+            v1 := l_shift(i_num(0), i_val,  1);
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+            v2 := l_shift(i_num(1), v1,     2);
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+            v3 := l_shift(i_num(2), v2,     4);
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+            v4 := l_shift(i_num(3), v3,     8);
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+            v5 := l_shift(i_num(4), v4,    16);
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+        ELSE
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+            v1 := r_shift(i_num(0), i_val, s_fill,  1);
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+            v2 := r_shift(i_num(1), v1,    s_fill,  2);
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+            v3 := r_shift(i_num(2), v2,    s_fill,  4);
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+            v4 := r_shift(i_num(3), v3,    s_fill,  8);
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+            v5 := r_shift(i_num(4), v4,    s_fill, 16);
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+        END IF;
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+        IF i_num(31 DOWNTO 5) = zero THEN
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+            o_val <= v5;
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+        ELSE
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+            o_val <= (OTHERS => s_fill);
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+        END IF;
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+    END PROCESS p_shift;
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+
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+END ARCHITECTURE a_mips_shifter;
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+
mips/types.vhd
View file @ 0a29d2e
... ... 
@@ -39,6 +39,7 @@ PACKAGE mips_types IS
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         alu_sra,  -- shift right arithmetically
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         alu_srl,  -- shift right logically
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         alu_slt,  -- set on less than
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+        alu_sltu, -- set on less than unsigned
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         alu_xor   -- bitwise XOR
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     );
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mips_sys.xise
View file @ 0a29d2e
... ... 
@@ -17,7 +17,7 @@
17 17 
   <files>
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     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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     </file>
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     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
... ... 
@@ -25,11 +25,11 @@
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     </file>
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     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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     </file>
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     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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     </file>
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     <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
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       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
... ... 
@@ -39,6 +39,10 @@
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     </file>
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     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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+    </file>
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+    <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
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+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
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       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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     </file>
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   </files>
45 49