implemented ethernet RX frame detection (41147d3) - mips_sys · BlinkenArea

implemented ethernet RX frame detection

Stefan Schuermans commited on 2012-03-03 16:13:53
Showing 6 changed files, with 294 additions and 58 deletions.

fw/eth.c 5f366eb..a540e5f
fw/eth.h 0c85e09..a34ce0f
fw/main.c 0dac46e..bd3c224
io/eth/eth.vhd 5a05ce7..c03d4db
io/eth/rxframe.vhd 0000000..4583867
mips_sys.xise cb2aef9..2cb3e85

fw/eth.c

@@ -13,13 +13,13 @@ int eth_can_rx(void)
 }
 
 /**
- * @brief receive a character
- * @return character received
+ * @brief receive a word
+ * @return word received
  */
-unsigned char eth_rx(void)
+unsigned int eth_rx(void)
 {
   while (!eth_ptr[0]);
-  unsigned char chr = eth_ptr[4];
-  return chr;
+  unsigned int w = *(volatile unsigned int *)(eth_ptr + 4);
+  return w;
 }
 

fw/eth.h

View file @ 41147d3

@@ -8,10 +8,10 @@
 int eth_can_rx(void);
 
 /**
- * @brief receive a character
- * @return character received
+ * @brief receive a word
+ * @return word received
  */
-unsigned char eth_rx(void);
+unsigned int eth_rx(void);
 
 #endif /* #ifndef ETH_H */
 

fw/main.c

View file @ 41147d3

@@ -51,15 +51,18 @@ void delay(void)
 {
   unsigned int i;
 #ifdef CFG_ETH
-  unsigned char chr;
+  unsigned int w;
 #endif
   for (i = 0; i < 10; ++i) {
     switches();
 #ifdef CFG_ETH
   while (eth_can_rx()) {
-    chr = eth_rx();
+    w = eth_rx();
 #ifdef CFG_UART
-  uart_tx(chr);
+  uart_tx(w);
+  uart_tx(w >> 8);
+  uart_tx(w >> 16);
+  uart_tx(w >> 24);
 #endif
   }
 #endif

io/eth/eth.vhd

View file @ 41147d3

@@ -32,18 +32,23 @@ END ENTITY e_io_eth;
 
 ARCHITECTURE a_io_eth OF e_io_eth IS
 
-    SIGNAL s_rx_data:    std_logic_vector(7 DOWNTO 0);
-    SIGNAL s_rx_data_en: std_logic;
-    SIGNAL s_rx_done:    std_logic;
-    SIGNAL s_rx_err:     std_logic;
+    SIGNAL s_rxif_data:    std_logic_vector(7 DOWNTO 0);
+    SIGNAL s_rxif_data_en: std_logic;
+    SIGNAL s_rxif_done:    std_logic;
+    SIGNAL s_rxif_err:     std_logic;
+
+    SIGNAL s_rxframe_data:    std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_rxframe_data_en: std_logic;
+    SIGNAL s_rxframe_done:    std_logic;
+    SIGNAL s_rxframe_err:     std_logic;
 
     -- so far only for testing
-    SIGNAL s_rx_fifo_wr_rdy:  std_logic;
-    SIGNAL s_rx_fifo_wr_data: std_logic_vector(7 DOWNTO 0);
-    SIGNAL s_rx_fifo_wr_en:   std_logic;
-    SIGNAL s_rx_fifo_rd_rdy:  std_logic;
-    SIGNAL s_rx_fifo_rd_data: std_logic_vector(7 DOWNTO 0);
-    SIGNAL s_rx_fifo_rd_en:   std_logic;
+    SIGNAL s_rxfifo_wr_rdy:  std_logic;
+    SIGNAL s_rxfifo_wr_data: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_rxfifo_wr_en:   std_logic;
+    SIGNAL s_rxfifo_rd_rdy:  std_logic;
+    SIGNAL s_rxfifo_rd_data: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_rxfifo_rd_en:   std_logic;
 
     COMPONENT e_io_eth_rst IS
         PORT (
@@ -69,6 +74,22 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
         );
     END COMPONENT e_io_eth_rxif;
 
+    COMPONENT e_io_eth_rxframe IS
+        PORT (
+            rst:       IN  std_logic;
+            clk:       IN  std_logic;
+            i_data:    IN  std_logic_vector( 7 DOWNTO 0);
+            i_data_en: IN  std_logic;
+            i_done:    IN  std_logic;
+            i_err:     IN  std_logic;
+            i_mac:     IN  std_logic_vector(47 DOWNTO 0);
+            o_data:    OUT std_logic_vector(31 DOWNTO 0);
+            o_data_en: OUT std_logic;
+            o_done:    OUT std_logic;
+            o_err:     OUT std_logic
+        );
+    END COMPONENT e_io_eth_rxframe;
+
     -- so far only for testing
     COMPONENT e_block_fifo IS
         GENERIC (
@@ -102,10 +123,10 @@ BEGIN
         PORT MAP (
             rst          => rst,
             clk          => clk,
-            o_data       => s_rx_data,
-            o_data_en    => s_rx_data_en,
-            o_done       => s_rx_done,
-            o_err        => s_rx_err,
+            o_data       => s_rxif_data,
+            o_data_en    => s_rxif_data_en,
+            o_done       => s_rxif_done,
+            o_err        => s_rxif_err,
             pin_i_rx_clk => pin_i_rx_clk,
             pin_i_rxd    => pin_i_rxd,
             pin_i_rx_dv  => pin_i_rx_dv,
@@ -113,38 +134,53 @@ BEGIN
             pin_i_col    => pin_i_col
         );
 
+    rxframe: e_io_eth_rxframe
+        PORT MAP (
+            rst       => rst,
+            clk       => clk,
+            i_data    => s_rxif_data,
+            i_data_en => s_rxif_data_en,
+            i_done    => s_rxif_done,
+            i_err     => s_rxif_err,
+            i_mac     => X"070605040302",
+            o_data    => s_rxframe_data,
+            o_data_en => s_rxframe_data_en,
+            o_done    => s_rxframe_done,
+            o_err     => s_rxframe_err
+        );
+
     -- so far only for testing
-    p_rx_if2fifo: PROCESS (s_rx_data, s_rx_data_en, s_rx_done, s_rx_err)
+    p_rx_if2fifo: PROCESS (s_rxframe_data, s_rxframe_data_en, s_rxframe_done, s_rxframe_err)
     BEGIN
-        IF s_rx_err = '1' THEN
-            s_rx_fifo_wr_data <= X"EE";
-        ELSIF s_rx_done = '1' THEN
-            s_rx_fifo_wr_data <= X"DD";
+        IF s_rxframe_err = '1' THEN
+            s_rxfifo_wr_data <= X"EEEEEEEE";
+        ELSIF s_rxframe_done = '1' THEN
+            s_rxfifo_wr_data <= X"DDDDDDDD";
         ELSE
-            s_rx_fifo_wr_data <= s_rx_data;
+            s_rxfifo_wr_data <= s_rxframe_data;
         END IF;
-        s_rx_fifo_wr_en <= s_rx_data_en OR s_rx_done OR s_rx_err;
+        s_rxfifo_wr_en <= s_rxframe_data_en OR s_rxframe_done OR s_rxframe_err;
     END PROCESS p_rx_if2fifo;
 
     -- so far only for testing
     rx_fifo: e_block_fifo
         GENERIC MAP (
-            addr_width => 11,
-            data_width => 8
+            addr_width => 9,
+            data_width => 32
         )
         PORT MAP (
             rst       => rst,
             clk       => clk,
-            o_wr_rdy  => s_rx_fifo_wr_rdy,
-            i_wr_data => s_rx_fifo_wr_data,
-            i_wr_en   => s_rx_fifo_wr_en,
-            o_rd_rdy  => s_rx_fifo_rd_rdy,
-            o_rd_data => s_rx_fifo_rd_data,
-            i_rd_en   => s_rx_fifo_rd_en
+            o_wr_rdy  => s_rxfifo_wr_rdy,
+            i_wr_data => s_rxfifo_wr_data,
+            i_wr_en   => s_rxfifo_wr_en,
+            o_rd_rdy  => s_rxfifo_rd_rdy,
+            o_rd_data => s_rxfifo_rd_data,
+            i_rd_en   => s_rxfifo_rd_en
         );
 
     -- so far only for testing
-    s_rx_fifo_rd_en <= '1' WHEN i_addr = "01" AND i_rd_en(0) = '1' ELSE '0';
+    s_rxfifo_rd_en <= '1' WHEN i_addr = "01" AND i_rd_en(0) = '1' ELSE '0';
 
     -- so far only for testing
     p_rx_test_rd: PROCESS (rst, clk)
@@ -154,9 +190,9 @@ BEGIN
         ELSIF rising_edge(clk) THEN
             o_rd_data       <= X"00000000";
             IF i_addr = "00" THEN
-                o_rd_data(0) <= s_rx_fifo_rd_rdy;
+                o_rd_data(0) <= s_rxfifo_rd_rdy;
             ELSIF i_addr = "01" THEN
-                o_rd_data(7 DOWNTO 0) <= s_rx_fifo_rd_data;
+                o_rd_data <= s_rxfifo_rd_data;
             END IF;
         END IF;
     END PROCESS p_rx_test_rd;

io/eth/rxframe.vhd

View file @ 41147d3

...	...	@@ -0,0 +1,193 @@
	1	+LIBRARY IEEE;
	2	+USE IEEE.STD_LOGIC_1164.ALL;
	3	+USE IEEE.NUMERIC_STD.ALL;
	4	+
	5	+ENTITY e_io_eth_rxframe IS
	6	+ PORT (
	7	+ rst: IN std_logic;
	8	+ clk: IN std_logic;
	9	+ i_data: IN std_logic_vector( 7 DOWNTO 0);
	10	+ i_data_en: IN std_logic;
	11	+ i_done: IN std_logic;
	12	+ i_err: IN std_logic;
	13	+ i_mac: IN std_logic_vector(47 DOWNTO 0);
	14	+ o_data: OUT std_logic_vector(31 DOWNTO 0);
	15	+ o_data_en: OUT std_logic;
	16	+ o_done: OUT std_logic;
	17	+ o_err: OUT std_logic
	18	+ );
	19	+END ENTITY e_io_eth_rxframe;
	20	+
	21	+ARCHITECTURE a_io_eth_rxframe OF e_io_eth_rxframe IS
	22	+
	23	+ TYPE t_state IS (st_idle, st_sync, st_mac, st_mac_uni, st_mac_brd, st_data);
	24	+
	25	+ SUBTYPE t_mac_cnt IS natural RANGE 0 TO 5;
	26	+ SUBTYPE t_data_cnt IS natural RANGE 0 TO 3;
	27	+
	28	+ SIGNAL r_state: t_state := st_idle;
	29	+ SIGNAL n_state: t_state;
	30	+ SIGNAL r_mac_cnt: t_mac_cnt := 0;
	31	+ SIGNAL n_mac_cnt: t_mac_cnt;
	32	+ SIGNAL r_data_cnt: t_data_cnt := 0;
	33	+ SIGNAL n_data_cnt: t_data_cnt;
	34	+
	35	+ SIGNAL r_out_data: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
	36	+ SIGNAL n_out_data: std_logic_vector(31 DOWNTO 0);
	37	+ SIGNAL r_out_data_en: std_logic := '0';
	38	+ SIGNAL n_out_data_en: std_logic;
	39	+ SIGNAL r_out_done: std_logic := '0';
	40	+ SIGNAL n_out_done: std_logic;
	41	+ SIGNAL r_out_err: std_logic := '0';
	42	+ SIGNAL n_out_err: std_logic;
	43	+
	44	+BEGIN
	45	+
	46	+ p_next: PROCESS(r_state, r_mac_cnt, r_data_cnt, r_out_data,
	47	+ i_data, i_data_en, i_done, i_err, i_mac)
	48	+ VARIABLE v_mac: std_logic_vector(7 DOWNTO 0);
	49	+ VARIABLE v_data: boolean;
	50	+ BEGIN
	51	+ n_state <= r_state;
	52	+ n_mac_cnt <= r_mac_cnt;
	53	+ n_data_cnt <= r_data_cnt;
	54	+ n_out_data <= r_out_data;
	55	+ n_out_data_en <= '0';
	56	+ n_out_done <= '0';
	57	+ n_out_err <= '0';
	58	+ v_data := false;
	59	+ CASE r_state IS
	60	+ WHEN st_idle =>
	61	+ IF i_data_en = '1' AND i_data = X"55" THEN
	62	+ n_state <= st_sync;
	63	+ END IF;
	64	+ WHEN st_sync =>
	65	+ IF i_data_en = '1' THEN
	66	+ IF i_data = X"D5" THEN
	67	+ n_state <= st_mac;
	68	+ n_mac_cnt <= 0;
	69	+ n_data_cnt <= 0;
	70	+ ELSIF i_data /= X"55" THEN
	71	+ n_state <= st_idle;
	72	+ END IF;
	73	+ ELSIF i_done = '1' OR i_err = '1' THEN
	74	+ n_state <= st_idle;
	75	+ END IF;
	76	+ WHEN st_mac =>
	77	+ IF i_data_en = '1' THEN
	78	+ v_mac := i_mac(7 + 8 * r_mac_cnt DOWNTO 8 * r_mac_cnt);
	79	+ IF v_mac = X"FF" THEN
	80	+ IF i_data = v_mac THEN
	81	+ v_data := true;
	82	+ ELSE
	83	+ n_state <= st_idle;
	84	+ n_out_err <= '1';
	85	+ END IF;
	86	+ ELSE
	87	+ IF i_data = v_mac THEN
	88	+ v_data := true;
	89	+ n_state <= st_mac_uni;
	90	+ ELSIF i_data = X"FF" THEN
	91	+ v_data := true;
	92	+ n_state <= st_mac_brd;
	93	+ ELSE
	94	+ n_state <= st_idle;
	95	+ n_out_err <= '1';
	96	+ END IF;
	97	+ END IF;
	98	+ IF r_mac_cnt < 5 THEN
	99	+ n_mac_cnt <= r_mac_cnt + 1;
	100	+ ELSE
	101	+ n_state <= st_data;
	102	+ END IF;
	103	+ ELSIF i_done = '1' OR i_err = '1' THEN
	104	+ n_state <= st_idle;
	105	+ n_out_err <= '1';
	106	+ END IF;
	107	+ WHEN st_mac_uni =>
	108	+ IF i_data_en = '1' THEN
	109	+ v_mac := i_mac(7 + 8 * r_mac_cnt DOWNTO 8 * r_mac_cnt);
	110	+ IF i_data = v_mac THEN
	111	+ v_data := true;
	112	+ ELSE
	113	+ n_state <= st_idle;
	114	+ n_out_err <= '1';
	115	+ END IF;
	116	+ IF r_mac_cnt < 5 THEN
	117	+ n_mac_cnt <= r_mac_cnt + 1;
	118	+ ELSE
	119	+ n_state <= st_data;
	120	+ END IF;
	121	+ ELSIF i_done = '1' OR i_err = '1' THEN
	122	+ n_state <= st_idle;
	123	+ n_out_err <= '1';
	124	+ END IF;
	125	+ WHEN st_mac_brd =>
	126	+ IF i_data_en = '1' THEN
	127	+ IF i_data = X"FF" THEN
	128	+ v_data := true;
	129	+ ELSE
	130	+ n_state <= st_idle;
	131	+ n_out_err <= '1';
	132	+ END IF;
	133	+ IF r_mac_cnt < 5 THEN
	134	+ n_mac_cnt <= r_mac_cnt + 1;
	135	+ ELSE
	136	+ n_state <= st_data;
	137	+ END IF;
	138	+ ELSIF i_done = '1' OR i_err = '1' THEN
	139	+ n_state <= st_idle;
	140	+ n_out_err <= '1';
	141	+ END IF;
	142	+ WHEN st_data =>
	143	+ IF i_data_en = '1' THEN
	144	+ v_data := true;
	145	+ ELSIF i_done = '1' THEN
	146	+ n_state <= st_idle;
	147	+ n_out_done <= '1';
	148	+ ELSIF i_err = '1' THEN
	149	+ n_state <= st_idle;
	150	+ n_out_err <= '1';
	151	+ END IF;
	152	+ WHEN OTHERS => NULL;
	153	+ END CASE;
	154	+ IF v_data THEN
	155	+ n_out_data(31 DOWNTO 24) <= i_data;
	156	+ n_out_data(23 DOWNTO 0) <= r_out_data(31 DOWNTO 8);
	157	+ IF r_data_cnt < 3 THEN
	158	+ n_data_cnt <= r_data_cnt + 1;
	159	+ ELSE
	160	+ n_data_cnt <= 0;
	161	+ n_out_data_en <= '1';
	162	+ END IF;
	163	+ END IF;
	164	+ END PROCESS p_next;
	165	+
	166	+ p_sync: PROCESS(rst, clk)
	167	+ BEGIN
	168	+ IF rst = '1' THEN
	169	+ r_state <= st_idle;
	170	+ r_mac_cnt <= 0;
	171	+ r_data_cnt <= 0;
	172	+ r_out_data <= (OTHERS => '0');
	173	+ r_out_data_en <= '0';
	174	+ r_out_done <= '0';
	175	+ r_out_err <= '0';
	176	+ ELSIF rising_edge(clk) THEN
	177	+ r_state <= n_state;
	178	+ r_mac_cnt <= n_mac_cnt;
	179	+ r_data_cnt <= n_data_cnt;
	180	+ r_out_data <= n_out_data;
	181	+ r_out_data_en <= n_out_data_en;
	182	+ r_out_done <= n_out_done;
	183	+ r_out_err <= n_out_err;
	184	+ END IF;
	185	+ END PROCESS p_sync;
	186	+
	187	+ o_data <= r_out_data;
	188	+ o_data_en <= r_out_data_en;
	189	+ o_done <= r_out_done;
	190	+ o_err <= r_out_err;
	191	+
	192	+END ARCHITECTURE a_io_eth_rxframe;
	193	+

mips_sys.xise

View file @ 41147d3

@@ -29,7 +29,7 @@
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
@@ -53,7 +53,7 @@
     </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
     </file>
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
@@ -63,11 +63,11 @@
     </file>
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -77,11 +77,11 @@
     </file>
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
@@ -92,19 +92,19 @@
     </file>
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
@@ -112,21 +112,21 @@
     </file>
     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
@@ -134,11 +134,11 @@
     </file>
     <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
@@ -151,6 +151,10 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="202"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+    </file>
   </files>
 
   <properties>


...	...	@@ -13,13 +13,13 @@ int eth_can_rx(void)
13	13	}
14	14
15	15	/**
16		- * @brief receive a character
17		- * @return character received
	16	+ * @brief receive a word
	17	+ * @return word received
18	18	*/
19		-unsigned char eth_rx(void)
	19	+unsigned int eth_rx(void)
20	20	{
21	21	while (!eth_ptr[0]);
22		- unsigned char chr = eth_ptr[4];
23		- return chr;
	22	+ unsigned int w = (volatile unsigned int )(eth_ptr + 4);
	23	+ return w;
24	24	}
25	25

...	...	@@ -8,10 +8,10 @@
8	8	int eth_can_rx(void);
9	9
10	10	/**
11		- * @brief receive a character
12		- * @return character received
	11	+ * @brief receive a word
	12	+ * @return word received
13	13	*/
14		-unsigned char eth_rx(void);
	14	+unsigned int eth_rx(void);
15	15
16	16	#endif /* #ifndef ETH_H */
17	17

...	...	@@ -51,15 +51,18 @@ void delay(void)
51	51	{
52	52	unsigned int i;
53	53	#ifdef CFG_ETH
54		- unsigned char chr;
	54	+ unsigned int w;
55	55	#endif
56	56	for (i = 0; i < 10; ++i) {
57	57	switches();
58	58	#ifdef CFG_ETH
59	59	while (eth_can_rx()) {
60		- chr = eth_rx();
	60	+ w = eth_rx();
61	61	#ifdef CFG_UART
62		- uart_tx(chr);
	62	+ uart_tx(w);
	63	+ uart_tx(w >> 8);
	64	+ uart_tx(w >> 16);
	65	+ uart_tx(w >> 24);
63	66	#endif
64	67	}
65	68	#endif

...	...	@@ -32,18 +32,23 @@ END ENTITY e_io_eth;
32	32
33	33	ARCHITECTURE a_io_eth OF e_io_eth IS
34	34
35		- SIGNAL s_rx_data: std_logic_vector(7 DOWNTO 0);
36		- SIGNAL s_rx_data_en: std_logic;
37		- SIGNAL s_rx_done: std_logic;
38		- SIGNAL s_rx_err: std_logic;
	35	+ SIGNAL s_rxif_data: std_logic_vector(7 DOWNTO 0);
	36	+ SIGNAL s_rxif_data_en: std_logic;
	37	+ SIGNAL s_rxif_done: std_logic;
	38	+ SIGNAL s_rxif_err: std_logic;
	39	+
	40	+ SIGNAL s_rxframe_data: std_logic_vector(31 DOWNTO 0);
	41	+ SIGNAL s_rxframe_data_en: std_logic;
	42	+ SIGNAL s_rxframe_done: std_logic;
	43	+ SIGNAL s_rxframe_err: std_logic;
39	44
40	45	-- so far only for testing
41		- SIGNAL s_rx_fifo_wr_rdy: std_logic;
42		- SIGNAL s_rx_fifo_wr_data: std_logic_vector(7 DOWNTO 0);
43		- SIGNAL s_rx_fifo_wr_en: std_logic;
44		- SIGNAL s_rx_fifo_rd_rdy: std_logic;
45		- SIGNAL s_rx_fifo_rd_data: std_logic_vector(7 DOWNTO 0);
46		- SIGNAL s_rx_fifo_rd_en: std_logic;
	46	+ SIGNAL s_rxfifo_wr_rdy: std_logic;
	47	+ SIGNAL s_rxfifo_wr_data: std_logic_vector(31 DOWNTO 0);
	48	+ SIGNAL s_rxfifo_wr_en: std_logic;
	49	+ SIGNAL s_rxfifo_rd_rdy: std_logic;
	50	+ SIGNAL s_rxfifo_rd_data: std_logic_vector(31 DOWNTO 0);
	51	+ SIGNAL s_rxfifo_rd_en: std_logic;
47	52
48	53	COMPONENT e_io_eth_rst IS
49	54	PORT (
...	...	@@ -69,6 +74,22 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
69	74	);
70	75	END COMPONENT e_io_eth_rxif;
71	76
	77	+ COMPONENT e_io_eth_rxframe IS
	78	+ PORT (
	79	+ rst: IN std_logic;
	80	+ clk: IN std_logic;
	81	+ i_data: IN std_logic_vector( 7 DOWNTO 0);
	82	+ i_data_en: IN std_logic;
	83	+ i_done: IN std_logic;
	84	+ i_err: IN std_logic;
	85	+ i_mac: IN std_logic_vector(47 DOWNTO 0);
	86	+ o_data: OUT std_logic_vector(31 DOWNTO 0);
	87	+ o_data_en: OUT std_logic;
	88	+ o_done: OUT std_logic;
	89	+ o_err: OUT std_logic
	90	+ );
	91	+ END COMPONENT e_io_eth_rxframe;
	92	+
72	93	-- so far only for testing
73	94	COMPONENT e_block_fifo IS
74	95	GENERIC (
...	...	@@ -102,10 +123,10 @@ BEGIN
102	123	PORT MAP (
103	124	rst => rst,
104	125	clk => clk,
105		- o_data => s_rx_data,
106		- o_data_en => s_rx_data_en,
107		- o_done => s_rx_done,
108		- o_err => s_rx_err,
	126	+ o_data => s_rxif_data,
	127	+ o_data_en => s_rxif_data_en,
	128	+ o_done => s_rxif_done,
	129	+ o_err => s_rxif_err,
109	130	pin_i_rx_clk => pin_i_rx_clk,
110	131	pin_i_rxd => pin_i_rxd,
111	132	pin_i_rx_dv => pin_i_rx_dv,
...	...	@@ -113,38 +134,53 @@ BEGIN
113	134	pin_i_col => pin_i_col
114	135	);
115	136
	137	+ rxframe: e_io_eth_rxframe
	138	+ PORT MAP (
	139	+ rst => rst,
	140	+ clk => clk,
	141	+ i_data => s_rxif_data,
	142	+ i_data_en => s_rxif_data_en,
	143	+ i_done => s_rxif_done,
	144	+ i_err => s_rxif_err,
	145	+ i_mac => X"070605040302",
	146	+ o_data => s_rxframe_data,
	147	+ o_data_en => s_rxframe_data_en,
	148	+ o_done => s_rxframe_done,
	149	+ o_err => s_rxframe_err
	150	+ );
	151	+
116	152	-- so far only for testing
117		- p_rx_if2fifo: PROCESS (s_rx_data, s_rx_data_en, s_rx_done, s_rx_err)
	153	+ p_rx_if2fifo: PROCESS (s_rxframe_data, s_rxframe_data_en, s_rxframe_done, s_rxframe_err)
118	154	BEGIN
119		- IF s_rx_err = '1' THEN
120		- s_rx_fifo_wr_data <= X"EE";
121		- ELSIF s_rx_done = '1' THEN
122		- s_rx_fifo_wr_data <= X"DD";
	155	+ IF s_rxframe_err = '1' THEN
	156	+ s_rxfifo_wr_data <= X"EEEEEEEE";
	157	+ ELSIF s_rxframe_done = '1' THEN
	158	+ s_rxfifo_wr_data <= X"DDDDDDDD";
123	159	ELSE
124		- s_rx_fifo_wr_data <= s_rx_data;
	160	+ s_rxfifo_wr_data <= s_rxframe_data;
125	161	END IF;
126		- s_rx_fifo_wr_en <= s_rx_data_en OR s_rx_done OR s_rx_err;
	162	+ s_rxfifo_wr_en <= s_rxframe_data_en OR s_rxframe_done OR s_rxframe_err;
127	163	END PROCESS p_rx_if2fifo;
128	164
129	165	-- so far only for testing
130	166	rx_fifo: e_block_fifo
131	167	GENERIC MAP (
132		- addr_width => 11,
133		- data_width => 8
	168	+ addr_width => 9,
	169	+ data_width => 32
134	170	)
135	171	PORT MAP (
136	172	rst => rst,
137	173	clk => clk,
138		- o_wr_rdy => s_rx_fifo_wr_rdy,
139		- i_wr_data => s_rx_fifo_wr_data,
140		- i_wr_en => s_rx_fifo_wr_en,
141		- o_rd_rdy => s_rx_fifo_rd_rdy,
142		- o_rd_data => s_rx_fifo_rd_data,
143		- i_rd_en => s_rx_fifo_rd_en
	174	+ o_wr_rdy => s_rxfifo_wr_rdy,
	175	+ i_wr_data => s_rxfifo_wr_data,
	176	+ i_wr_en => s_rxfifo_wr_en,
	177	+ o_rd_rdy => s_rxfifo_rd_rdy,
	178	+ o_rd_data => s_rxfifo_rd_data,
	179	+ i_rd_en => s_rxfifo_rd_en
144	180	);
145	181
146	182	-- so far only for testing
147		- s_rx_fifo_rd_en <= '1' WHEN i_addr = "01" AND i_rd_en(0) = '1' ELSE '0';
	183	+ s_rxfifo_rd_en <= '1' WHEN i_addr = "01" AND i_rd_en(0) = '1' ELSE '0';
148	184
149	185	-- so far only for testing
150	186	p_rx_test_rd: PROCESS (rst, clk)
...	...	@@ -154,9 +190,9 @@ BEGIN
154	190	ELSIF rising_edge(clk) THEN
155	191	o_rd_data <= X"00000000";
156	192	IF i_addr = "00" THEN
157		- o_rd_data(0) <= s_rx_fifo_rd_rdy;
	193	+ o_rd_data(0) <= s_rxfifo_rd_rdy;
158	194	ELSIF i_addr = "01" THEN
159		- o_rd_data(7 DOWNTO 0) <= s_rx_fifo_rd_data;
	195	+ o_rd_data <= s_rxfifo_rd_data;
160	196	END IF;
161	197	END IF;
162	198	END PROCESS p_rx_test_rd;

...	...	@@ -29,7 +29,7 @@
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31	31	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
32		- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
	32	+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
33	33	</file>
34	34	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35	35	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
...	...	@@ -53,7 +53,7 @@
53	53	</file>
54	54	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55	55	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
56		- <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
	56	+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
57	57	</file>
58	58	<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59	59	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
...	...	@@ -63,11 +63,11 @@
63	63	</file>
64	64	<file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65	65	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
66		- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
	66	+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
67	67	</file>
68	68	<file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69	69	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
70		- <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
	70	+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
71	71	</file>
72	72	<file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
73	73	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...	...	@@ -77,11 +77,11 @@
77	77	</file>
78	78	<file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
79	79	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
80		- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
	80	+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
81	81	</file>
82	82	<file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
83	83	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
84		- <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
	84	+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
85	85	</file>
86	86	<file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
87	87	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
...	...	@@ -92,19 +92,19 @@
92	92	</file>
93	93	<file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
94	94	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
95		- <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
	95	+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
96	96	</file>
97	97	<file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
98	98	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
99		- <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
	99	+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
100	100	</file>
101	101	<file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
102	102	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
103		- <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
	103	+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
104	104	</file>
105	105	<file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
106	106	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
107		- <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
	107	+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
108	108	</file>
109	109	<file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
110	110	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
...	...	@@ -112,21 +112,21 @@
112	112	</file>
113	113	<file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
114	114	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
115		- <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
	115	+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
116	116	</file>
117	117	<file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118	118	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119	119	</file>
120	120	<file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
121	121	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
122		- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
	122	+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
123	123	</file>
124	124	<file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
125	125	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
126	126	</file>
127	127	<file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
128	128	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
129		- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
	129	+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
130	130	</file>
131	131	<file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
132	132	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
...	...	@@ -134,11 +134,11 @@
134	134	</file>
135	135	<file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
136	136	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
137		- <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
	137	+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
138	138	</file>
139	139	<file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
140	140	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
141		- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
	141	+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
142	142	</file>
143	143	<file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
144	144	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
...	...	@@ -151,6 +151,10 @@
151	151	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
152	152	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
153	153	</file>
	154	+ <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
	155	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="202"/>
	156	+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
	157	+ </file>
154	158	</files>
155	159
156	160	<properties>
157	161