implemented loading of data memory from firmware (0e00df4) - mips_sys · BlinkenArea

implemented loading of data memory from firmware

Stefan Schuermans commited on 2012-02-12 17:47:50
Showing 11 changed files, with 272 additions and 123 deletions.

fw/.gitignore 72ba3b1..b70bf6b
fw/Makefile 214a772..371c8ff
fw/lnk.cmd c6b4d41..8049f84
fw/main.c a9b7f38..3503bec
fw/ram.pl 0000000..8d7d9f8
fw/rom.head.vhd 44b0396..0000000
fw/rom.pl 0000000..f28dd82
fw/rom.tail.vhd 65dc39f..0000000
mips_sys.xise 9539236..d77af8f
system/ram.vhd 7a1e646..0000000
system/system.vhd 29f9050..6d9d80f

fw/.gitignore

...	...	@@ -2,5 +2,7 @@
2	2	*.o
3	3	deps
4	4	fw
5		-fw.bin
	5	+ram.[0-3].vhd
	6	+ram.bin
	7	+rom.bin
6	8	rom.vhd

fw/Makefile

View file @ 0e00df4

@@ -1,5 +1,6 @@
 SRCS=cyc_cnt.c lcd.c leds.c main.c
 
+PERL=perl
 CC=mipsel-elf-gcc
 LD=mipsel-elf-ld
 OBJCOPY=mipsel-elf-objcopy
@@ -11,8 +12,10 @@ DEPS=$(addsuffix .d,$(BASES))
 OBJS=$(addsuffix .o,$(BASES))
 
 .PHONY: all clean
+.SUFFIXES:
+.SECONDARY:
 
-all: rom.vhd
+all: rom.vhd ram.0.vhd ram.1.vhd ram.2.vhd ram.3.vhd
 
 ifneq ($(MAKECMDGOALS),clean)
   include deps
@@ -36,17 +39,18 @@ fw.o: $(OBJS)
 fw: lnk.cmd boot.o fw.o
 	$(LD) $(LFLAGS) -T lnk.cmd -o $@ boot.o fw.o
 
-fw.bin: fw
-	$(OBJCOPY) -j .text -O binary $< $@
+%.bin: fw
+	$(OBJCOPY) -j .$(basename $@) -O binary $< $@
 
-rom.vhd: rom.head.vhd rom.tail.vhd fw.bin
-	cat rom.head.vhd >$@
-	hexdump -e '1/4 "%08X\n"' -v fw.bin | \
-	  sed 's/^/=> X"/;s/$$/",/' | \
-	  nl -p -v 0 | \
-	  sed 's/^/        /' >>$@
-	cat rom.tail.vhd >>$@
+rom.vhd: rom.pl rom.bin
+	$(PERL) rom.pl rom.bin >$@
+
+ram.%.vhd: ram.pl ram.bin
+	$(PERL) ram.pl ram.bin $(patsubst ram.%.vhd,%,$@) >$@
 
 clean:
-	rm -f $(OBJS) boot.o fw.o fw fw.bin rom.vhd
+	rm -f $(DEPS) $(OBJS)
+	rm -f boot.o fw.o fw
+	rm -f rom.bin rom.vhd
+	rm -f ram.bin ram.[0-3].vhd
 

fw/lnk.cmd

View file @ 0e00df4

...	...	@@ -1,9 +1,8 @@
1	1	SECTIONS
2	2	{
3	3	. = 0x00000000;
4		- .text : { *(.text) }
	4	+ .rom : { *(.text) }
5	5	. = 0x00001000;
6		- .data : { *(.data) }
7		- .bss : { *(.bss) }
	6	+ .ram : { (.rodata) (.data) (.bss) (COM) }
8	7	}
9	8

fw/main.c

View file @ 0e00df4

@@ -2,6 +2,10 @@
 #include "lcd.h"
 #include "leds.h"
 
+const int myconst = 0x12345678;
+
+int myvar = 0x11223344;
+
 volatile int data[100];
 
 void delay(void)

fw/ram.pl

View file @ 0e00df4

...	...	@@ -0,0 +1,70 @@
	1	+#! /usr/bin/perl
	2	+
	3	+use strict;
	4	+use warnings;
	5	+
	6	+if (@ARGV < 2) {
	7	+ die "usage: $0 <binary file> <ram number>\n";
	8	+}
	9	+my $binfile = $ARGV[0];
	10	+my $ramno = abs(int($ARGV[1]));
	11	+
	12	+open BINFILE, "<", $binfile or die "cannot read \"$binfile\": ";
	13	+binmode BINFILE;
	14	+
	15	+print <<EOF;
	16	+LIBRARY IEEE;
	17	+USE IEEE.STD_LOGIC_1164.ALL;
	18	+USE IEEE.NUMERIC_STD.ALL;
	19	+
	20	+ENTITY e_ram_$ramno IS
	21	+ GENERIC (
	22	+ addr_width: natural
	23	+ );
	24	+ PORT (
	25	+ clk: IN std_logic;
	26	+ i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	27	+ o_rd_data: OUT std_logic_vector( 7 DOWNTO 0);
	28	+ i_wr_data: IN std_logic_vector( 7 DOWNTO 0);
	29	+ i_wr_en: IN std_logic
	30	+ );
	31	+END ENTITY e_ram_$ramno;
	32	+
	33	+ARCHITECTURE a_ram_$ramno OF e_ram_$ramno IS
	34	+
	35	+ SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
	36	+ SUBTYPE t_data IS std_logic_vector( 7 DOWNTO 0);
	37	+ TYPE t_buf IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
	38	+
	39	+ SIGNAL s_buf: t_buf := (
	40	+EOF
	41	+
	42	+my $addr = 0;
	43	+my $data;
	44	+while (read(BINFILE, $data, 4)) {
	45	+ my @d = unpack("CCCC", $data);
	46	+ printf " %d => X\"%02X\",\n", $addr, $d[$ramno];
	47	+ ++$addr;
	48	+}
	49	+
	50	+print <<EOF;
	51	+ OTHERS => X"00"
	52	+ );
	53	+
	54	+BEGIN
	55	+
	56	+ p_ram: PROCESS(clk)
	57	+ BEGIN
	58	+ IF rising_edge(clk) THEN
	59	+ IF i_wr_en = '1' THEN
	60	+ s_buf(to_integer(unsigned(i_addr))) <= i_wr_data;
	61	+ END IF;
	62	+ o_rd_data <= s_buf(to_integer(unsigned(i_addr)));
	63	+ END IF;
	64	+ END PROCESS p_ram;
	65	+
	66	+END ARCHITECTURE a_ram_$ramno;
	67	+EOF
	68	+
	69	+close BINFILE;
	70	+

fw/rom.head.vhd

View file @ df6d296

@@ -1,22 +0,0 @@
                         -LIBRARY IEEE;
                         -USE IEEE.STD_LOGIC_1164.ALL;
                         -USE IEEE.NUMERIC_STD.ALL;
+                        -
                         -ENTITY e_rom IS
                         -    GENERIC (
                         -        addr_width: INTEGER
                         -    );
                         -    PORT (
                         -        clk:    IN  std_logic;
                         -        i_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
                         -        o_data: OUT std_logic_vector(            31 DOWNTO 0)
                         -    );
                         -END ENTITY e_rom;
+                        -
                         -ARCHITECTURE a_rom OF e_rom IS
+                        -
                         -    SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
                         -    SUBTYPE t_data IS std_logic_vector(            31 DOWNTO 0);
                         -    TYPE    t_buf  IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
+                        -
                         -    SIGNAL s_buf: t_buf := (

fw/rom.pl

View file @ 0e00df4

...	...	@@ -0,0 +1,63 @@
	1	+#! /usr/bin/perl
	2	+
	3	+use strict;
	4	+use warnings;
	5	+
	6	+if (@ARGV < 1) {
	7	+ die "usage: $0 <binary file>\n";
	8	+}
	9	+my $binfile = $ARGV[0];
	10	+
	11	+open BINFILE, "<", $binfile or die "cannot read \"$binfile\": ";
	12	+binmode BINFILE;
	13	+
	14	+print <<EOF;
	15	+LIBRARY IEEE;
	16	+USE IEEE.STD_LOGIC_1164.ALL;
	17	+USE IEEE.NUMERIC_STD.ALL;
	18	+
	19	+ENTITY e_rom IS
	20	+ GENERIC (
	21	+ addr_width: natural
	22	+ );
	23	+ PORT (
	24	+ clk: IN std_logic;
	25	+ i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	26	+ o_data: OUT std_logic_vector( 31 DOWNTO 0)
	27	+ );
	28	+END ENTITY e_rom;
	29	+
	30	+ARCHITECTURE a_rom OF e_rom IS
	31	+
	32	+ SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
	33	+ SUBTYPE t_data IS std_logic_vector( 31 DOWNTO 0);
	34	+ TYPE t_buf IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
	35	+
	36	+ SIGNAL s_buf: t_buf := (
	37	+EOF
	38	+
	39	+my $addr = 0;
	40	+my $data;
	41	+while (read(BINFILE, $data, 4)) {
	42	+ my @d = unpack("CCCC", $data);
	43	+ printf " %d => X\"%02X%02X%02X%02X\",\n",
	44	+ $addr, $d[3], $d[2], $d[1], $d[0];
	45	+ ++$addr;
	46	+}
	47	+
	48	+print <<EOF;
	49	+ OTHERS => X"00000000"
	50	+ );
	51	+
	52	+BEGIN
	53	+
	54	+ p_rom: PROCESS(clk)
	55	+ BEGIN
	56	+ IF rising_edge(clk) THEN
	57	+ o_data <= s_buf(to_integer(unsigned(i_addr)));
	58	+ END IF;
	59	+ END PROCESS p_rom;
	60	+
	61	+END ARCHITECTURE a_rom;
	62	+EOF
	63	+

fw/rom.tail.vhd

View file @ df6d296

@@ -1,14 +0,0 @@
                         -        OTHERS => X"00000000"
                         -    );
+                        -
                         -BEGIN
+                        -
                         -    p_rom: PROCESS(clk)
                         -    BEGIN
                         -        IF rising_edge(clk) THEN
                         -            o_data <= s_buf(to_integer(unsigned(i_addr)));
                         -        END IF;
                         -    END PROCESS p_rom;
+                        -
                         -END ARCHITECTURE a_rom;
+                        -

mips_sys.xise

View file @ 0e00df4

@@ -28,8 +28,8 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
@@ -51,27 +51,23 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
-    <file xil_pn:name="system/ram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
-    </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
     </file>
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -83,13 +79,13 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
-    </file>
-    <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
+    <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+    </file>
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
@@ -97,6 +93,22 @@
     <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+    </file>
+    <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+    </file>
+    <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+    </file>
+    <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+    </file>
   </files>
 
   <properties>

system/ram.vhd

View file @ df6d296

@@ -1,40 +0,0 @@
                         -LIBRARY IEEE;
                         -USE IEEE.STD_LOGIC_1164.ALL;
                         -USE IEEE.NUMERIC_STD.ALL;
+                        -
                         -ENTITY e_ram IS
                         -    GENERIC (
                         -        addr_width: natural;
                         -        data_width: natural
                         -    );
                         -    PORT (
                         -        clk:       IN  std_logic;
                         -        i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
                         -        o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
                         -        i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
                         -        i_wr_en:   IN  std_logic
                         -    );
                         -END ENTITY e_ram;
+                        -
                         -ARCHITECTURE a_ram OF e_ram IS
+                        -
                         -    SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
                         -    SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
                         -    TYPE    t_buf  IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
+                        -
                         -    SIGNAL s_buf: t_buf;
+                        -
                         -BEGIN
+                        -
                         -    p_ram: PROCESS(clk)
                         -    BEGIN
                         -        IF rising_edge(clk) THEN
                         -            IF i_wr_en = '1' THEN
                         -                s_buf(to_integer(unsigned(i_addr))) <= i_wr_data;
                         -            END IF;
                         -            o_rd_data <= s_buf(to_integer(unsigned(i_addr)));
                         -        END IF;
                         -    END PROCESS p_ram;
+                        -
                         -END ARCHITECTURE a_ram;
+                        -

system/system.vhd

View file @ 0e00df4

@@ -50,7 +50,7 @@ ARCHITECTURE a_system OF e_system IS
 
     COMPONENT e_rom IS
         GENERIC (
-            addr_width: INTEGER
+            addr_width: natural
         );
         PORT (
             clk:    IN  std_logic;
@@ -59,19 +59,57 @@ ARCHITECTURE a_system OF e_system IS
         );
     END COMPONENT e_rom;
 
-    COMPONENT e_ram IS
+    COMPONENT e_ram_0 IS
         GENERIC (
-            addr_width: natural;
-            data_width: natural
+            addr_width: natural
         );
         PORT (
             clk:       IN  std_logic;
             i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
-            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
-            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
+            o_rd_data: OUT std_logic_vector(             7 DOWNTO 0);
+            i_wr_data: IN  std_logic_vector(             7 DOWNTO 0);
             i_wr_en:   IN  std_logic
         );
-    END COMPONENT e_ram;
+    END COMPONENT e_ram_0;
+
+    COMPONENT e_ram_1 IS
+        GENERIC (
+            addr_width: natural
+        );
+        PORT (
+            clk:       IN  std_logic;
+            i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
+            o_rd_data: OUT std_logic_vector(             7 DOWNTO 0);
+            i_wr_data: IN  std_logic_vector(             7 DOWNTO 0);
+            i_wr_en:   IN  std_logic
+        );
+    END COMPONENT e_ram_1;
+
+    COMPONENT e_ram_2 IS
+        GENERIC (
+            addr_width: natural
+        );
+        PORT (
+            clk:       IN  std_logic;
+            i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
+            o_rd_data: OUT std_logic_vector(             7 DOWNTO 0);
+            i_wr_data: IN  std_logic_vector(             7 DOWNTO 0);
+            i_wr_en:   IN  std_logic
+        );
+    END COMPONENT e_ram_2;
+
+    COMPONENT e_ram_3 IS
+        GENERIC (
+            addr_width: natural
+        );
+        PORT (
+            clk:       IN  std_logic;
+            i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
+            o_rd_data: OUT std_logic_vector(             7 DOWNTO 0);
+            i_wr_data: IN  std_logic_vector(             7 DOWNTO 0);
+            i_wr_en:   IN  std_logic
+        );
+    END COMPONENT e_ram_3;
 
     COMPONENT e_io_leds IS
         PORT (
@@ -173,20 +211,53 @@ BEGIN
         END IF;
     END PROCESS p_dbus;
 
-    data: FOR i IN 0 TO 3 GENERATE
-        databank: e_ram
+    data_0: e_ram_0
+        GENERIC MAP (
+            addr_width => 10
+        )
+        PORT MAP (
+            clk       => clk,
+            i_addr    => s_data_addr(11 DOWNTO 2),
+            o_rd_data => s_data_rd_data(7 DOWNTO 0),
+            i_wr_data => s_data_wr_data(7 DOWNTO 0),
+            i_wr_en   => s_data_wr_en(0)
+        );
+
+    data_1: e_ram_1
+        GENERIC MAP (
+            addr_width => 10
+        )
+        PORT MAP (
+            clk       => clk,
+            i_addr    => s_data_addr(11 DOWNTO 2),
+            o_rd_data => s_data_rd_data(15 DOWNTO 8),
+            i_wr_data => s_data_wr_data(15 DOWNTO 8),
+            i_wr_en   => s_data_wr_en(1)
+        );
+
+    data_2: e_ram_2
+        GENERIC MAP (
+            addr_width => 10
+        )
+        PORT MAP (
+            clk       => clk,
+            i_addr    => s_data_addr(11 DOWNTO 2),
+            o_rd_data => s_data_rd_data(23 DOWNTO 16),
+            i_wr_data => s_data_wr_data(23 DOWNTO 16),
+            i_wr_en   => s_data_wr_en(2)
+        );
+
+    data_3: e_ram_3
         GENERIC MAP (
-                addr_width => 10,
-                data_width => 8
+            addr_width => 10
         )
         PORT MAP (
             clk       => clk,
             i_addr    => s_data_addr(11 DOWNTO 2),
-                o_rd_data => s_data_rd_data(i*8+7 DOWNTO i*8),
-                i_wr_data => s_data_wr_data(i*8+7 DOWNTO i*8),
-                i_wr_en   => s_data_wr_en(i)
+            o_rd_data => s_data_rd_data(31 DOWNTO 24),
+            i_wr_data => s_data_wr_data(31 DOWNTO 24),
+            i_wr_en   => s_data_wr_en(3)
         );
-    END GENERATE data;
 
     leds: e_io_leds
         PORT MAP (


...	...	@@ -1,5 +1,6 @@
1	1	SRCS=cyc_cnt.c lcd.c leds.c main.c
2	2
	3	+PERL=perl
3	4	CC=mipsel-elf-gcc
4	5	LD=mipsel-elf-ld
5	6	OBJCOPY=mipsel-elf-objcopy
...	...	@@ -11,8 +12,10 @@ DEPS=$(addsuffix .d,$(BASES))
11	12	OBJS=$(addsuffix .o,$(BASES))
12	13
13	14	.PHONY: all clean
	15	+.SUFFIXES:
	16	+.SECONDARY:
14	17
15		-all: rom.vhd
	18	+all: rom.vhd ram.0.vhd ram.1.vhd ram.2.vhd ram.3.vhd
16	19
17	20	ifneq ($(MAKECMDGOALS),clean)
18	21	include deps
...	...	@@ -36,17 +39,18 @@ fw.o: $(OBJS)
36	39	fw: lnk.cmd boot.o fw.o
37	40	$(LD) $(LFLAGS) -T lnk.cmd -o $@ boot.o fw.o
38	41
39		-fw.bin: fw
40		- $(OBJCOPY) -j .text -O binary $< $@
	42	+%.bin: fw
	43	+ $(OBJCOPY) -j .$(basename $@) -O binary $< $@
41	44
42		-rom.vhd: rom.head.vhd rom.tail.vhd fw.bin
43		- cat rom.head.vhd >$@
44		- hexdump -e '1/4 "%08X\n"' -v fw.bin \| \
45		- sed 's/^/=> X"/;s/$$/",/' \| \
46		- nl -p -v 0 \| \
47		- sed 's/^/ /' >>$@
48		- cat rom.tail.vhd >>$@
	45	+rom.vhd: rom.pl rom.bin
	46	+ $(PERL) rom.pl rom.bin >$@
	47	+
	48	+ram.%.vhd: ram.pl ram.bin
	49	+ $(PERL) ram.pl ram.bin $(patsubst ram.%.vhd,%,$@) >$@
49	50
50	51	clean:
51		- rm -f $(OBJS) boot.o fw.o fw fw.bin rom.vhd
	52	+ rm -f $(DEPS) $(OBJS)
	53	+ rm -f boot.o fw.o fw
	54	+ rm -f rom.bin rom.vhd
	55	+ rm -f ram.bin ram.[0-3].vhd
52	56

...	...	@@ -2,6 +2,10 @@
2	2	#include "lcd.h"
3	3	#include "leds.h"
4	4
	5	+const int myconst = 0x12345678;
	6	+
	7	+int myvar = 0x11223344;
	8	+
5	9	volatile int data[100];
6	10
7	11	void delay(void)

...	...	@@ -28,8 +28,8 @@
28	28	<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
32		- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
	31	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
	32	+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
33	33	</file>
34	34	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35	35	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
...	...	@@ -51,27 +51,23 @@
51	51	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
52	52	<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
53	53	</file>
54		- <file xil_pn:name="system/ram.vhd" xil_pn:type="FILE_VHDL">
55		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
56		- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
57		- </file>
58	54	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
59		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
60		- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
	55	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
	56	+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
61	57	</file>
62	58	<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
63		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
	59	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
64	60	<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
65	61	<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
66	62	<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
67	63	</file>
68	64	<file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
69		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
70		- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
	65	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
	66	+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
71	67	</file>
72	68	<file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
73		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
74		- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
	69	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
	70	+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
75	71	</file>
76	72	<file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
77	73	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...	...	@@ -83,13 +79,13 @@
83	79	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
84	80	</file>
85	81	<file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
86		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
87		- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
88		- </file>
89		- <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
90	82	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
91	83	<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
92	84	</file>
	85	+ <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
	86	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
	87	+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
	88	+ </file>
93	89	<file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
94	90	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
95	91	<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
...	...	@@ -97,6 +93,22 @@
97	93	<file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
98	94	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
99	95	</file>
	96	+ <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
	97	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
	98	+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
	99	+ </file>
	100	+ <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
	101	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
	102	+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
	103	+ </file>
	104	+ <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
	105	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
	106	+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
	107	+ </file>
	108	+ <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
	109	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
	110	+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
	111	+ </file>
100	112	</files>
101	113
102	114	<properties>

...	...	@@ -50,7 +50,7 @@ ARCHITECTURE a_system OF e_system IS
50	50
51	51	COMPONENT e_rom IS
52	52	GENERIC (
53		- addr_width: INTEGER
	53	+ addr_width: natural
54	54	);
55	55	PORT (
56	56	clk: IN std_logic;
...	...	@@ -59,19 +59,57 @@ ARCHITECTURE a_system OF e_system IS
59	59	);
60	60	END COMPONENT e_rom;
61	61
62		- COMPONENT e_ram IS
	62	+ COMPONENT e_ram_0 IS
63	63	GENERIC (
64		- addr_width: natural;
65		- data_width: natural
	64	+ addr_width: natural
66	65	);
67	66	PORT (
68	67	clk: IN std_logic;
69	68	i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
70		- o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
71		- i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
	69	+ o_rd_data: OUT std_logic_vector( 7 DOWNTO 0);
	70	+ i_wr_data: IN std_logic_vector( 7 DOWNTO 0);
72	71	i_wr_en: IN std_logic
73	72	);
74		- END COMPONENT e_ram;
	73	+ END COMPONENT e_ram_0;
	74	+
	75	+ COMPONENT e_ram_1 IS
	76	+ GENERIC (
	77	+ addr_width: natural
	78	+ );
	79	+ PORT (
	80	+ clk: IN std_logic;
	81	+ i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	82	+ o_rd_data: OUT std_logic_vector( 7 DOWNTO 0);
	83	+ i_wr_data: IN std_logic_vector( 7 DOWNTO 0);
	84	+ i_wr_en: IN std_logic
	85	+ );
	86	+ END COMPONENT e_ram_1;
	87	+
	88	+ COMPONENT e_ram_2 IS
	89	+ GENERIC (
	90	+ addr_width: natural
	91	+ );
	92	+ PORT (
	93	+ clk: IN std_logic;
	94	+ i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	95	+ o_rd_data: OUT std_logic_vector( 7 DOWNTO 0);
	96	+ i_wr_data: IN std_logic_vector( 7 DOWNTO 0);
	97	+ i_wr_en: IN std_logic
	98	+ );
	99	+ END COMPONENT e_ram_2;
	100	+
	101	+ COMPONENT e_ram_3 IS
	102	+ GENERIC (
	103	+ addr_width: natural
	104	+ );
	105	+ PORT (
	106	+ clk: IN std_logic;
	107	+ i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	108	+ o_rd_data: OUT std_logic_vector( 7 DOWNTO 0);
	109	+ i_wr_data: IN std_logic_vector( 7 DOWNTO 0);
	110	+ i_wr_en: IN std_logic
	111	+ );
	112	+ END COMPONENT e_ram_3;
75	113
76	114	COMPONENT e_io_leds IS
77	115	PORT (
...	...	@@ -173,20 +211,53 @@ BEGIN
173	211	END IF;
174	212	END PROCESS p_dbus;
175	213
176		- data: FOR i IN 0 TO 3 GENERATE
177		- databank: e_ram
	214	+ data_0: e_ram_0
	215	+ GENERIC MAP (
	216	+ addr_width => 10
	217	+ )
	218	+ PORT MAP (
	219	+ clk => clk,
	220	+ i_addr => s_data_addr(11 DOWNTO 2),
	221	+ o_rd_data => s_data_rd_data(7 DOWNTO 0),
	222	+ i_wr_data => s_data_wr_data(7 DOWNTO 0),
	223	+ i_wr_en => s_data_wr_en(0)
	224	+ );
	225	+
	226	+ data_1: e_ram_1
	227	+ GENERIC MAP (
	228	+ addr_width => 10
	229	+ )
	230	+ PORT MAP (
	231	+ clk => clk,
	232	+ i_addr => s_data_addr(11 DOWNTO 2),
	233	+ o_rd_data => s_data_rd_data(15 DOWNTO 8),
	234	+ i_wr_data => s_data_wr_data(15 DOWNTO 8),
	235	+ i_wr_en => s_data_wr_en(1)
	236	+ );
	237	+
	238	+ data_2: e_ram_2
	239	+ GENERIC MAP (
	240	+ addr_width => 10
	241	+ )
	242	+ PORT MAP (
	243	+ clk => clk,
	244	+ i_addr => s_data_addr(11 DOWNTO 2),
	245	+ o_rd_data => s_data_rd_data(23 DOWNTO 16),
	246	+ i_wr_data => s_data_wr_data(23 DOWNTO 16),
	247	+ i_wr_en => s_data_wr_en(2)
	248	+ );
	249	+
	250	+ data_3: e_ram_3
178	251	GENERIC MAP (
179		- addr_width => 10,
180		- data_width => 8
	252	+ addr_width => 10
181	253	)
182	254	PORT MAP (
183	255	clk => clk,
184	256	i_addr => s_data_addr(11 DOWNTO 2),
185		- o_rd_data => s_data_rd_data(i8+7 DOWNTO i8),
186		- i_wr_data => s_data_wr_data(i8+7 DOWNTO i8),
187		- i_wr_en => s_data_wr_en(i)
	257	+ o_rd_data => s_data_rd_data(31 DOWNTO 24),
	258	+ i_wr_data => s_data_wr_data(31 DOWNTO 24),
	259	+ i_wr_en => s_data_wr_en(3)
188	260	);
189		- END GENERATE data;
190	261
191	262	leds: e_io_leds
192	263	PORT MAP (
193	264