MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
second version of multiplier (slower, i.e. more stages -> faster clock)
9225422 @ 2012-02-05 21:39:45
| constraints | start of MIPS core: begin of decoder and ALU | 2012-01-23 22:06:18 |
|---|---|---|
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| mips | second version of multiplier (slower, i.e. more stages -> faster clock) | 2012-02-05 21:39:45 |
| .gitignore | start of MIPS core: begin of decoder and ALU | 2012-01-23 22:06:18 |
| mips_sys.xise | second version of multiplier (slower, i.e. more stages -> faster clock) | 2012-02-05 21:39:45 |