implemented ethernet RX busmaster -> packet reception working
Stefan Schuermans commited on 2012-03-03 23:42:55
Showing 11 changed files, with 416 additions and 184 deletions.
- Default.wcfg f36b2f4..278517c
- fw/eth.c a540e5f..d46cd7b
- fw/eth.h a34ce0f..c84ffc0
- fw/lnk.cmd 4a8485a..427ef99
- fw/main.c bd3c224..653513e
- io/eth/eth.vhd c03d4db..cd450e7
- io/eth/rxframe.vhd 6b0191b..1495553
- mips_sys.xise 8698316..e883192
- stuff/eth_pack.hex 0000000..abb5252
- stuff/eth_pack.nib 0000000..ab21461
- system/system.vhd 8081592..22049ec
| ... | ... |
@@ -23,6 +23,7 @@ |
| 23 | 23 |
<wvobject fp_name="/e_testbed/pin_leds" type="array" db_ref_id="1"> |
| 24 | 24 |
<obj_property name="ElementShortName">pin_leds[7:0]</obj_property> |
| 25 | 25 |
<obj_property name="ObjectShortName">pin_leds[7:0]</obj_property> |
| 26 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 26 | 27 |
</wvobject> |
| 27 | 28 |
<wvobject fp_name="/e_testbed/pin_lcd" type="array" db_ref_id="1"> |
| 28 | 29 |
<obj_property name="ElementShortName">pin_lcd</obj_property> |
| ... | ... |
@@ -36,11 +37,6 @@ |
| 36 | 37 |
<obj_property name="ElementShortName">pin_o_uart_tx</obj_property> |
| 37 | 38 |
<obj_property name="ObjectShortName">pin_o_uart_tx</obj_property> |
| 38 | 39 |
</wvobject> |
| 39 |
- <wvobject fp_name="/e_testbed/system/core/regs/r_regs[29]" type="array" db_ref_id="1"> |
|
| 40 |
- <obj_property name="ElementShortName">[29]</obj_property> |
|
| 41 |
- <obj_property name="ObjectShortName">r_regs[29]</obj_property> |
|
| 42 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 43 |
- </wvobject> |
|
| 44 | 40 |
<wvobject fp_name="/e_testbed/system/core/o_instr_addr" type="array" db_ref_id="1"> |
| 45 | 41 |
<obj_property name="ElementShortName">o_instr_addr[31:0]</obj_property> |
| 46 | 42 |
<obj_property name="ObjectShortName">o_instr_addr[31:0]</obj_property> |
| ... | ... |
@@ -55,80 +51,94 @@ |
| 55 | 51 |
<obj_property name="ElementShortName">s_stall</obj_property> |
| 56 | 52 |
<obj_property name="ObjectShortName">s_stall</obj_property> |
| 57 | 53 |
</wvobject> |
| 58 |
- <wvobject fp_name="/e_testbed/system/s_core_req" type="logic" db_ref_id="1"> |
|
| 59 |
- <obj_property name="ElementShortName">s_core_req</obj_property> |
|
| 60 |
- <obj_property name="ObjectShortName">s_core_req</obj_property> |
|
| 54 |
+ <wvobject fp_name="/e_testbed/system/eth/r_rx_start" type="array" db_ref_id="1"> |
|
| 55 |
+ <obj_property name="ElementShortName">r_rx_start[31:0]</obj_property> |
|
| 56 |
+ <obj_property name="ObjectShortName">r_rx_start[31:0]</obj_property> |
|
| 57 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 61 | 58 |
</wvobject> |
| 62 |
- <wvobject fp_name="/e_testbed/system/s_core_grant" type="logic" db_ref_id="1"> |
|
| 63 |
- <obj_property name="ElementShortName">s_core_grant</obj_property> |
|
| 64 |
- <obj_property name="ObjectShortName">s_core_grant</obj_property> |
|
| 59 |
+ <wvobject fp_name="/e_testbed/system/eth/r_rx_cur" type="array" db_ref_id="1"> |
|
| 60 |
+ <obj_property name="ElementShortName">r_rx_cur[31:0]</obj_property> |
|
| 61 |
+ <obj_property name="ObjectShortName">r_rx_cur[31:0]</obj_property> |
|
| 62 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 63 |
+ </wvobject> |
|
| 64 |
+ <wvobject fp_name="/e_testbed/system/eth/r_rx_size" type="array" db_ref_id="1"> |
|
| 65 |
+ <obj_property name="ElementShortName">r_rx_size[31:0]</obj_property> |
|
| 66 |
+ <obj_property name="ObjectShortName">r_rx_size[31:0]</obj_property> |
|
| 67 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 65 | 68 |
</wvobject> |
| 66 |
- <wvobject fp_name="/e_testbed/system/s_core_addr" type="array" db_ref_id="1"> |
|
| 67 |
- <obj_property name="ElementShortName">s_core_addr[31:0]</obj_property> |
|
| 68 |
- <obj_property name="ObjectShortName">s_core_addr[31:0]</obj_property> |
|
| 69 |
+ <wvobject fp_name="/e_testbed/system/eth/r_rx_end" type="array" db_ref_id="1"> |
|
| 70 |
+ <obj_property name="ElementShortName">r_rx_end[31:0]</obj_property> |
|
| 71 |
+ <obj_property name="ObjectShortName">r_rx_end[31:0]</obj_property> |
|
| 72 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 69 | 73 |
</wvobject> |
| 70 |
- <wvobject fp_name="/e_testbed/system/s_core_rd_data" type="array" db_ref_id="1"> |
|
| 71 |
- <obj_property name="ElementShortName">s_core_rd_data[31:0]</obj_property> |
|
| 72 |
- <obj_property name="ObjectShortName">s_core_rd_data[31:0]</obj_property> |
|
| 74 |
+ <wvobject fp_name="/e_testbed/system/eth/r_rx_new_start" type="array" db_ref_id="1"> |
|
| 75 |
+ <obj_property name="ElementShortName">r_rx_new_start[31:0]</obj_property> |
|
| 76 |
+ <obj_property name="ObjectShortName">r_rx_new_start[31:0]</obj_property> |
|
| 77 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 73 | 78 |
</wvobject> |
| 74 |
- <wvobject fp_name="/e_testbed/system/s_core_rd_en" type="array" db_ref_id="1"> |
|
| 75 |
- <obj_property name="ElementShortName">s_core_rd_en[3:0]</obj_property> |
|
| 76 |
- <obj_property name="ObjectShortName">s_core_rd_en[3:0]</obj_property> |
|
| 79 |
+ <wvobject fp_name="/e_testbed/system/eth/r_rx_new_end" type="array" db_ref_id="1"> |
|
| 80 |
+ <obj_property name="ElementShortName">r_rx_new_end[31:0]</obj_property> |
|
| 81 |
+ <obj_property name="ObjectShortName">r_rx_new_end[31:0]</obj_property> |
|
| 82 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 77 | 83 |
</wvobject> |
| 78 |
- <wvobject fp_name="/e_testbed/system/s_core_wr_data" type="array" db_ref_id="1"> |
|
| 79 |
- <obj_property name="ElementShortName">s_core_wr_data[31:0]</obj_property> |
|
| 80 |
- <obj_property name="ObjectShortName">s_core_wr_data[31:0]</obj_property> |
|
| 84 |
+ <wvobject fp_name="/e_testbed/system/eth/r_rx_new_en" type="logic" db_ref_id="1"> |
|
| 85 |
+ <obj_property name="ElementShortName">r_rx_new_en</obj_property> |
|
| 86 |
+ <obj_property name="ObjectShortName">r_rx_new_en</obj_property> |
|
| 81 | 87 |
</wvobject> |
| 82 |
- <wvobject fp_name="/e_testbed/system/s_core_wr_en" type="array" db_ref_id="1"> |
|
| 83 |
- <obj_property name="ElementShortName">s_core_wr_en[3:0]</obj_property> |
|
| 84 |
- <obj_property name="ObjectShortName">s_core_wr_en[3:0]</obj_property> |
|
| 88 |
+ <wvobject fp_name="/e_testbed/system/eth/s_rx_new" type="logic" db_ref_id="1"> |
|
| 89 |
+ <obj_property name="ElementShortName">s_rx_new</obj_property> |
|
| 90 |
+ <obj_property name="ObjectShortName">s_rx_new</obj_property> |
|
| 85 | 91 |
</wvobject> |
| 86 |
- <wvobject fp_name="/e_testbed/system/s_ethbm_req" type="logic" db_ref_id="1"> |
|
| 87 |
- <obj_property name="ElementShortName">s_ethbm_req</obj_property> |
|
| 88 |
- <obj_property name="ObjectShortName">s_ethbm_req</obj_property> |
|
| 92 |
+ <wvobject fp_name="/e_testbed/system/core/o_data_req" type="logic" db_ref_id="1"> |
|
| 93 |
+ <obj_property name="ElementShortName">o_data_req</obj_property> |
|
| 94 |
+ <obj_property name="ObjectShortName">o_data_req</obj_property> |
|
| 89 | 95 |
</wvobject> |
| 90 |
- <wvobject fp_name="/e_testbed/system/s_ethbm_grant" type="logic" db_ref_id="1"> |
|
| 91 |
- <obj_property name="ElementShortName">s_ethbm_grant</obj_property> |
|
| 92 |
- <obj_property name="ObjectShortName">s_ethbm_grant</obj_property> |
|
| 96 |
+ <wvobject fp_name="/e_testbed/system/core/i_data_grant" type="logic" db_ref_id="1"> |
|
| 97 |
+ <obj_property name="ElementShortName">i_data_grant</obj_property> |
|
| 98 |
+ <obj_property name="ObjectShortName">i_data_grant</obj_property> |
|
| 93 | 99 |
</wvobject> |
| 94 |
- <wvobject fp_name="/e_testbed/system/s_ethbm_addr" type="array" db_ref_id="1"> |
|
| 95 |
- <obj_property name="ElementShortName">s_ethbm_addr[31:0]</obj_property> |
|
| 96 |
- <obj_property name="ObjectShortName">s_ethbm_addr[31:0]</obj_property> |
|
| 100 |
+ <wvobject fp_name="/e_testbed/system/core/o_data_addr" type="array" db_ref_id="1"> |
|
| 101 |
+ <obj_property name="ElementShortName">o_data_addr[31:0]</obj_property> |
|
| 102 |
+ <obj_property name="ObjectShortName">o_data_addr[31:0]</obj_property> |
|
| 103 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 97 | 104 |
</wvobject> |
| 98 |
- <wvobject fp_name="/e_testbed/system/s_ethbm_rd_data" type="array" db_ref_id="1"> |
|
| 99 |
- <obj_property name="ElementShortName">s_ethbm_rd_data[31:0]</obj_property> |
|
| 100 |
- <obj_property name="ObjectShortName">s_ethbm_rd_data[31:0]</obj_property> |
|
| 105 |
+ <wvobject fp_name="/e_testbed/system/core/o_data_wr_data" type="array" db_ref_id="1"> |
|
| 106 |
+ <obj_property name="ElementShortName">o_data_wr_data[31:0]</obj_property> |
|
| 107 |
+ <obj_property name="ObjectShortName">o_data_wr_data[31:0]</obj_property> |
|
| 108 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 101 | 109 |
</wvobject> |
| 102 |
- <wvobject fp_name="/e_testbed/system/s_ethbm_rd_en" type="array" db_ref_id="1"> |
|
| 103 |
- <obj_property name="ElementShortName">s_ethbm_rd_en[3:0]</obj_property> |
|
| 104 |
- <obj_property name="ObjectShortName">s_ethbm_rd_en[3:0]</obj_property> |
|
| 110 |
+ <wvobject fp_name="/e_testbed/system/core/o_data_wr_en" type="array" db_ref_id="1"> |
|
| 111 |
+ <obj_property name="ElementShortName">o_data_wr_en[3:0]</obj_property> |
|
| 112 |
+ <obj_property name="ObjectShortName">o_data_wr_en[3:0]</obj_property> |
|
| 105 | 113 |
</wvobject> |
| 106 |
- <wvobject fp_name="/e_testbed/system/s_ethbm_wr_data" type="array" db_ref_id="1"> |
|
| 107 |
- <obj_property name="ElementShortName">s_ethbm_wr_data[31:0]</obj_property> |
|
| 108 |
- <obj_property name="ObjectShortName">s_ethbm_wr_data[31:0]</obj_property> |
|
| 114 |
+ <wvobject fp_name="/e_testbed/system/core/i_data_rd_data" type="array" db_ref_id="1"> |
|
| 115 |
+ <obj_property name="ElementShortName">i_data_rd_data[31:0]</obj_property> |
|
| 116 |
+ <obj_property name="ObjectShortName">i_data_rd_data[31:0]</obj_property> |
|
| 117 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 109 | 118 |
</wvobject> |
| 110 |
- <wvobject fp_name="/e_testbed/system/s_ethbm_wr_en" type="array" db_ref_id="1"> |
|
| 111 |
- <obj_property name="ElementShortName">s_ethbm_wr_en[3:0]</obj_property> |
|
| 112 |
- <obj_property name="ObjectShortName">s_ethbm_wr_en[3:0]</obj_property> |
|
| 119 |
+ <wvobject fp_name="/e_testbed/system/core/o_data_rd_en" type="array" db_ref_id="1"> |
|
| 120 |
+ <obj_property name="ElementShortName">o_data_rd_en[3:0]</obj_property> |
|
| 121 |
+ <obj_property name="ObjectShortName">o_data_rd_en[3:0]</obj_property> |
|
| 113 | 122 |
</wvobject> |
| 114 |
- <wvobject fp_name="/e_testbed/system/s_dbus_addr" type="array" db_ref_id="1"> |
|
| 115 |
- <obj_property name="ElementShortName">s_dbus_addr[31:0]</obj_property> |
|
| 116 |
- <obj_property name="ObjectShortName">s_dbus_addr[31:0]</obj_property> |
|
| 123 |
+ <wvobject fp_name="/e_testbed/system/eth/o_bm_req" type="logic" db_ref_id="1"> |
|
| 124 |
+ <obj_property name="ElementShortName">o_bm_req</obj_property> |
|
| 125 |
+ <obj_property name="ObjectShortName">o_bm_req</obj_property> |
|
| 117 | 126 |
</wvobject> |
| 118 |
- <wvobject fp_name="/e_testbed/system/s_dbus_rd_data" type="array" db_ref_id="1"> |
|
| 119 |
- <obj_property name="ElementShortName">s_dbus_rd_data[31:0]</obj_property> |
|
| 120 |
- <obj_property name="ObjectShortName">s_dbus_rd_data[31:0]</obj_property> |
|
| 127 |
+ <wvobject fp_name="/e_testbed/system/eth/i_bm_grant" type="logic" db_ref_id="1"> |
|
| 128 |
+ <obj_property name="ElementShortName">i_bm_grant</obj_property> |
|
| 129 |
+ <obj_property name="ObjectShortName">i_bm_grant</obj_property> |
|
| 121 | 130 |
</wvobject> |
| 122 |
- <wvobject fp_name="/e_testbed/system/s_dbus_rd_en" type="array" db_ref_id="1"> |
|
| 123 |
- <obj_property name="ElementShortName">s_dbus_rd_en[3:0]</obj_property> |
|
| 124 |
- <obj_property name="ObjectShortName">s_dbus_rd_en[3:0]</obj_property> |
|
| 131 |
+ <wvobject fp_name="/e_testbed/system/eth/o_bm_addr" type="array" db_ref_id="1"> |
|
| 132 |
+ <obj_property name="ElementShortName">o_bm_addr[31:0]</obj_property> |
|
| 133 |
+ <obj_property name="ObjectShortName">o_bm_addr[31:0]</obj_property> |
|
| 134 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 125 | 135 |
</wvobject> |
| 126 |
- <wvobject fp_name="/e_testbed/system/s_dbus_wr_data" type="array" db_ref_id="1"> |
|
| 127 |
- <obj_property name="ElementShortName">s_dbus_wr_data[31:0]</obj_property> |
|
| 128 |
- <obj_property name="ObjectShortName">s_dbus_wr_data[31:0]</obj_property> |
|
| 136 |
+ <wvobject fp_name="/e_testbed/system/eth/o_bm_wr_en" type="array" db_ref_id="1"> |
|
| 137 |
+ <obj_property name="ElementShortName">o_bm_wr_en[3:0]</obj_property> |
|
| 138 |
+ <obj_property name="ObjectShortName">o_bm_wr_en[3:0]</obj_property> |
|
| 129 | 139 |
</wvobject> |
| 130 |
- <wvobject fp_name="/e_testbed/system/s_dbus_wr_en" type="array" db_ref_id="1"> |
|
| 131 |
- <obj_property name="ElementShortName">s_dbus_wr_en[3:0]</obj_property> |
|
| 132 |
- <obj_property name="ObjectShortName">s_dbus_wr_en[3:0]</obj_property> |
|
| 140 |
+ <wvobject fp_name="/e_testbed/system/eth/o_bm_rd_en" type="array" db_ref_id="1"> |
|
| 141 |
+ <obj_property name="ElementShortName">o_bm_rd_en[3:0]</obj_property> |
|
| 142 |
+ <obj_property name="ObjectShortName">o_bm_rd_en[3:0]</obj_property> |
|
| 133 | 143 |
</wvobject> |
| 134 | 144 |
</wave_config> |
| ... | ... |
@@ -1,25 +1,76 @@ |
| 1 | 1 |
#include "eth.h" |
| 2 | 2 |
|
| 3 |
-static volatile unsigned char *const eth_ptr = |
|
| 4 |
- (volatile unsigned char *)0x80000400; |
|
| 3 |
+static volatile unsigned int *const eth_ptr = |
|
| 4 |
+ (volatile unsigned int *)0x80000400; |
|
| 5 |
+ |
|
| 6 |
+static unsigned int eth_idx_hw; |
|
| 7 |
+static unsigned int eth_rx_buf[2][256]; |
|
| 8 |
+static unsigned int *eth_rx_pos; |
|
| 5 | 9 |
|
| 6 | 10 |
/** |
| 7 |
- * @brief check if receiving a character is possible |
|
| 8 |
- * @return if receiving a character is possible |
|
| 11 |
+ * @brief provide new receive buffer |
|
| 12 |
+ * @param[in] ptr pointer to new receive buffer |
|
| 13 |
+ * @param[in] sz size of new receive buffer |
|
| 9 | 14 |
*/ |
| 10 |
-int eth_can_rx(void) |
|
| 15 |
+static void eth_rx_new_buf(void *ptr, unsigned int sz) |
|
| 11 | 16 |
{
|
| 12 |
- return eth_ptr[0]; |
|
| 17 |
+ eth_ptr[4] = (unsigned int)ptr; /* new start */ |
|
| 18 |
+ eth_ptr[5] = (unsigned int)ptr + sz; /* new end */ |
|
| 19 |
+ eth_ptr[6] = 1; /* set flag */ |
|
| 20 |
+ while (eth_ptr[6] == 1); /* wait until processed */ |
|
| 13 | 21 |
} |
| 14 | 22 |
|
| 15 | 23 |
/** |
| 16 |
- * @brief receive a word |
|
| 17 |
- * @return word received |
|
| 24 |
+ * @brief get buffer position of ethernet receiver |
|
| 25 |
+ * @return current buffer position of ethernet receiver |
|
| 26 |
+ * |
|
| 27 |
+ * eveything before this position can be read |
|
| 18 | 28 |
*/ |
| 19 |
-unsigned int eth_rx(void) |
|
| 29 |
+static void * eth_rx_get_pos(void) |
|
| 30 |
+{
|
|
| 31 |
+ return (void *)eth_ptr[0]; |
|
| 32 |
+} |
|
| 33 |
+ |
|
| 34 |
+/** initialize receiver */ |
|
| 35 |
+void eth_rx_init(void) |
|
| 20 | 36 |
{
|
| 21 |
- while (!eth_ptr[0]); |
|
| 22 |
- unsigned int w = *(volatile unsigned int *)(eth_ptr + 4); |
|
| 23 |
- return w; |
|
| 37 |
+ // give buffer 0 to HW |
|
| 38 |
+ eth_idx_hw = 0; |
|
| 39 |
+ eth_rx_new_buf(eth_rx_buf[0], sizeof(eth_rx_buf[0])); |
|
| 40 |
+ // buffer 1 owned by SW is empty |
|
| 41 |
+ eth_rx_buf[1][0] = 0; |
|
| 42 |
+ eth_rx_pos = eth_rx_buf[1]; |
|
| 43 |
+} |
|
| 44 |
+ |
|
| 45 |
+/** |
|
| 46 |
+ * @brief get next received packet |
|
| 47 |
+ * @param[out] *pptr pointer to packet data |
|
| 48 |
+ * @param[out] *psz size of packet |
|
| 49 |
+ * @return if a packet was received |
|
| 50 |
+ */ |
|
| 51 |
+int eth_rx(void **pptr, unsigned int *psz) |
|
| 52 |
+{
|
|
| 53 |
+ // current SW buffer is empty and HW buffer contains a packet |
|
| 54 |
+ if (*eth_rx_pos == 0 && eth_rx_get_pos() != eth_rx_buf[eth_idx_hw]) {
|
|
| 55 |
+ // swap buffers |
|
| 56 |
+ eth_idx_hw = 1 - eth_idx_hw; |
|
| 57 |
+ // give new HW buffer to HW |
|
| 58 |
+ eth_rx_new_buf(eth_rx_buf[eth_idx_hw], sizeof(eth_rx_buf[eth_idx_hw])); |
|
| 59 |
+ // start reading packet data at begin of new SW buffer |
|
| 60 |
+ eth_rx_pos = eth_rx_buf[1 - eth_idx_hw]; |
|
| 61 |
+ } |
|
| 62 |
+ |
|
| 63 |
+ // SW buffer contains a packet |
|
| 64 |
+ if (*eth_rx_pos > 0) {
|
|
| 65 |
+ // return size and pointer, advance position |
|
| 66 |
+ *psz = *eth_rx_pos; |
|
| 67 |
+ eth_rx_pos++; |
|
| 68 |
+ *pptr = eth_rx_pos; |
|
| 69 |
+ eth_rx_pos += *psz >> 2; |
|
| 70 |
+ return 1; |
|
| 71 |
+ } |
|
| 72 |
+ |
|
| 73 |
+ // no packet received |
|
| 74 |
+ return 0; |
|
| 24 | 75 |
} |
| 25 | 76 |
|
| ... | ... |
@@ -1,17 +1,16 @@ |
| 1 | 1 |
#ifndef ETH_H |
| 2 | 2 |
#define ETH_H |
| 3 | 3 |
|
| 4 |
-/** |
|
| 5 |
- * @brief check if receiving a character is possible |
|
| 6 |
- * @return if receiving a character is possible |
|
| 7 |
- */ |
|
| 8 |
-int eth_can_rx(void); |
|
| 4 |
+/** initialize receiver */ |
|
| 5 |
+void eth_rx_init(void); |
|
| 9 | 6 |
|
| 10 | 7 |
/** |
| 11 |
- * @brief receive a word |
|
| 12 |
- * @return word received |
|
| 8 |
+ * @brief get next received packet |
|
| 9 |
+ * @param[out] *pptr pointer to packet data |
|
| 10 |
+ * @param[out] *psz size of packet |
|
| 11 |
+ * @return if a packet was received |
|
| 13 | 12 |
*/ |
| 14 |
-unsigned int eth_rx(void); |
|
| 13 |
+int eth_rx(void **pptr, unsigned int *psz); |
|
| 15 | 14 |
|
| 16 | 15 |
#endif /* #ifndef ETH_H */ |
| 17 | 16 |
|
| ... | ... |
@@ -7,12 +7,12 @@ |
| 7 | 7 |
|
| 8 | 8 |
//#define CFG_SIMULATION |
| 9 | 9 |
|
| 10 |
+#define CFG_ETH |
|
| 10 | 11 |
#define CFG_UART |
| 11 | 12 |
#ifdef CFG_SIMULATION |
| 12 | 13 |
# define CFG_UART_CHK |
| 13 | 14 |
#else |
| 14 | 15 |
# define CFG_DELAY |
| 15 |
-# define CFG_ETH |
|
| 16 | 16 |
# define CFG_LCD |
| 17 | 17 |
#endif |
| 18 | 18 |
|
| ... | ... |
@@ -51,18 +51,16 @@ void delay(void) |
| 51 | 51 |
{
|
| 52 | 52 |
unsigned int i; |
| 53 | 53 |
#ifdef CFG_ETH |
| 54 |
- unsigned int w; |
|
| 54 |
+ unsigned int sz; |
|
| 55 |
+ unsigned char *ptr; |
|
| 55 | 56 |
#endif |
| 56 | 57 |
for (i = 0; i < 10; ++i) {
|
| 57 | 58 |
switches(); |
| 58 | 59 |
#ifdef CFG_ETH |
| 59 |
- while (eth_can_rx()) {
|
|
| 60 |
- w = eth_rx(); |
|
| 60 |
+ while (eth_rx(&ptr, &sz)) {
|
|
| 61 | 61 |
#ifdef CFG_UART |
| 62 |
- uart_tx(w); |
|
| 63 |
- uart_tx(w >> 8); |
|
| 64 |
- uart_tx(w >> 16); |
|
| 65 |
- uart_tx(w >> 24); |
|
| 62 |
+ for ( ; sz > 0; ptr++, sz--) |
|
| 63 |
+ uart_tx(*ptr); |
|
| 66 | 64 |
#endif |
| 67 | 65 |
} |
| 68 | 66 |
#endif |
| ... | ... |
@@ -78,15 +76,27 @@ int main() |
| 78 | 76 |
unsigned short chr; |
| 79 | 77 |
unsigned char leds; |
| 80 | 78 |
|
| 79 |
+ leds_set_state(0x01); |
|
| 80 |
+ |
|
| 81 | 81 |
for (i = 0; i < sizeof(data) / sizeof(data[0]); ++i) |
| 82 | 82 |
data[i] = i; |
| 83 | 83 |
|
| 84 |
+ leds_set_state(0x02); |
|
| 85 |
+ |
|
| 86 |
+#ifdef CFG_ETH |
|
| 87 |
+ eth_rx_init(); |
|
| 88 |
+#endif |
|
| 89 |
+ |
|
| 90 |
+ leds_set_state(0x04); |
|
| 91 |
+ |
|
| 84 | 92 |
#ifdef CFG_LCD |
| 85 | 93 |
lcd_init(); |
| 86 | 94 |
lcd_str(0, "MIPS I system"); |
| 87 | 95 |
lcd_str(1, ""); |
| 88 | 96 |
#endif |
| 89 | 97 |
|
| 98 |
+ leds_set_state(0x08); |
|
| 99 |
+ |
|
| 90 | 100 |
#ifdef CFG_UART |
| 91 | 101 |
uart_cfg_scale(62); /* 115200 */ |
| 92 | 102 |
uart_cfg_bits(8); |
| ... | ... |
@@ -111,6 +121,8 @@ int main() |
| 111 | 121 |
#endif |
| 112 | 122 |
#endif |
| 113 | 123 |
|
| 124 |
+ leds_set_state(0x10); |
|
| 125 |
+ |
|
| 114 | 126 |
leds = 0x11; |
| 115 | 127 |
while (1) {
|
| 116 | 128 |
#ifdef CFG_UART |
| ... | ... |
@@ -6,7 +6,7 @@ ENTITY e_io_eth IS |
| 6 | 6 |
PORT ( |
| 7 | 7 |
rst: IN std_logic; |
| 8 | 8 |
clk: IN std_logic; |
| 9 |
- i_addr: IN std_logic_vector( 1 DOWNTO 0); |
|
| 9 |
+ i_addr: IN std_logic_vector( 2 DOWNTO 0); |
|
| 10 | 10 |
o_rd_data: OUT std_logic_vector(31 DOWNTO 0); |
| 11 | 11 |
i_rd_en: IN std_logic_vector( 3 DOWNTO 0); |
| 12 | 12 |
i_wr_data: IN std_logic_vector(31 DOWNTO 0); |
| ... | ... |
@@ -42,13 +42,44 @@ ARCHITECTURE a_io_eth OF e_io_eth IS |
| 42 | 42 |
SIGNAL s_rxframe_done: std_logic; |
| 43 | 43 |
SIGNAL s_rxframe_err: std_logic; |
| 44 | 44 |
|
| 45 |
- -- so far only for testing |
|
| 46 |
- SIGNAL s_rxfifo_wr_rdy: std_logic; |
|
| 47 |
- SIGNAL s_rxfifo_wr_data: std_logic_vector(31 DOWNTO 0); |
|
| 48 |
- SIGNAL s_rxfifo_wr_en: std_logic; |
|
| 49 |
- SIGNAL s_rxfifo_rd_rdy: std_logic; |
|
| 50 |
- SIGNAL s_rxfifo_rd_data: std_logic_vector(31 DOWNTO 0); |
|
| 51 |
- SIGNAL s_rxfifo_rd_en: std_logic; |
|
| 45 |
+ -- RX buffer registers |
|
| 46 |
+ -- start: current buffer begin |
|
| 47 |
+ -- cur: address of next data write |
|
| 48 |
+ -- size: size of data received |
|
| 49 |
+ -- end: address just behind buffer |
|
| 50 |
+ -- data is written to buffer like this: <size><data 0>...<data size-1> |
|
| 51 |
+ -- size is written last |
|
| 52 |
+ -- next packet begins directly afterwards |
|
| 53 |
+ -- all addresses/sizes are word-aligned |
|
| 54 |
+ SIGNAL r_rx_start: std_logic_vector(31 DOWNTO 0) := X"00000000"; |
|
| 55 |
+ SIGNAL n_rx_start: std_logic_vector(31 DOWNTO 0); |
|
| 56 |
+ SIGNAL r_rx_cur: std_logic_vector(31 DOWNTO 0) := X"00000004"; |
|
| 57 |
+ SIGNAL n_rx_cur: std_logic_vector(31 DOWNTO 0); |
|
| 58 |
+ SIGNAL r_rx_size: std_logic_vector(31 DOWNTO 0) := X"00000000"; |
|
| 59 |
+ SIGNAL n_rx_size: std_logic_vector(31 DOWNTO 0); |
|
| 60 |
+ SIGNAL r_rx_end: std_logic_vector(31 DOWNTO 0) := X"00000000"; |
|
| 61 |
+ SIGNAL n_rx_end: std_logic_vector(31 DOWNTO 0); |
|
| 62 |
+ |
|
| 63 |
+ -- RX new buffer registers |
|
| 64 |
+ -- new_start: begin of new buffer |
|
| 65 |
+ -- new_end: address just behind new buffer |
|
| 66 |
+ -- new_en: if a new buffer is available |
|
| 67 |
+ -- all addresses are word-aligned |
|
| 68 |
+ SIGNAL r_rx_new_start: std_logic_vector(31 DOWNTO 0) := X"00000000"; |
|
| 69 |
+ SIGNAL n_rx_new_start: std_logic_vector(31 DOWNTO 0); |
|
| 70 |
+ SIGNAL r_rx_new_end: std_logic_vector(31 DOWNTO 0) := X"00000000"; |
|
| 71 |
+ SIGNAL n_rx_new_end: std_logic_vector(31 DOWNTO 0); |
|
| 72 |
+ SIGNAL r_rx_new_en: std_logic := '0'; |
|
| 73 |
+ SIGNAL n_rx_new_en: std_logic; |
|
| 74 |
+ |
|
| 75 |
+ SIGNAL s_rx_new: std_logic; |
|
| 76 |
+ |
|
| 77 |
+ SIGNAL s_wrbuf_wr_rdy: std_logic; |
|
| 78 |
+ SIGNAL s_wrbuf_wr_data: std_logic_vector(63 DOWNTO 0); |
|
| 79 |
+ SIGNAL s_wrbuf_wr_en: std_logic; |
|
| 80 |
+ SIGNAL s_wrbuf_rd_rdy: std_logic; |
|
| 81 |
+ SIGNAL s_wrbuf_rd_data: std_logic_vector(63 DOWNTO 0); |
|
| 82 |
+ SIGNAL s_wrbuf_rd_en: std_logic; |
|
| 52 | 83 |
|
| 53 | 84 |
COMPONENT e_io_eth_rst IS |
| 54 | 85 |
PORT ( |
| ... | ... |
@@ -90,7 +121,6 @@ ARCHITECTURE a_io_eth OF e_io_eth IS |
| 90 | 121 |
); |
| 91 | 122 |
END COMPONENT e_io_eth_rxframe; |
| 92 | 123 |
|
| 93 |
- -- so far only for testing |
|
| 94 | 124 |
COMPONENT e_block_fifo IS |
| 95 | 125 |
GENERIC ( |
| 96 | 126 |
addr_width: natural; |
| ... | ... |
@@ -108,8 +138,6 @@ ARCHITECTURE a_io_eth OF e_io_eth IS |
| 108 | 138 |
); |
| 109 | 139 |
END COMPONENT e_block_fifo; |
| 110 | 140 |
|
| 111 |
- SIGNAL r_cnt: natural := 0; |
|
| 112 |
- |
|
| 113 | 141 |
BEGIN |
| 114 | 142 |
|
| 115 | 143 |
reset: e_io_eth_rst |
| ... | ... |
@@ -149,77 +177,205 @@ BEGIN |
| 149 | 177 |
o_err => s_rxframe_err |
| 150 | 178 |
); |
| 151 | 179 |
|
| 152 |
- -- so far only for testing |
|
| 153 |
- p_rx_if2fifo: PROCESS (s_rxframe_data, s_rxframe_data_en, s_rxframe_done, s_rxframe_err) |
|
| 180 |
+ p_rx_next: PROCESS(r_rx_start, r_rx_cur, r_rx_size, r_rx_end, |
|
| 181 |
+ r_rx_new_start, r_rx_new_end, r_rx_new_en, |
|
| 182 |
+ s_rxframe_data, s_rxframe_data_en, |
|
| 183 |
+ s_rxframe_done, s_rxframe_err, |
|
| 184 |
+ s_wrbuf_wr_rdy) |
|
| 185 |
+ VARIABLE v_abort: boolean; -- abort current packet reception |
|
| 186 |
+ VARIABLE v_ignore: boolean; -- ignore rest of packet |
|
| 187 |
+ VARIABLE v_store: boolean; -- store packet data |
|
| 188 |
+ VARIABLE v_finish: boolean; -- finish reception of packet |
|
| 154 | 189 |
BEGIN |
| 155 |
- IF s_rxframe_err = '1' THEN |
|
| 156 |
- s_rxfifo_wr_data <= X"EEEEEEEE"; |
|
| 190 |
+ n_rx_start <= r_rx_start; |
|
| 191 |
+ n_rx_cur <= r_rx_cur; |
|
| 192 |
+ n_rx_size <= r_rx_size; |
|
| 193 |
+ n_rx_end <= r_rx_end; |
|
| 194 |
+ s_wrbuf_wr_data <= (OTHERS => '0'); |
|
| 195 |
+ s_wrbuf_wr_en <= '0'; |
|
| 196 |
+ s_rx_new <= '0'; |
|
| 197 |
+ |
|
| 198 |
+ -- determine which action to perform |
|
| 199 |
+ v_abort := false; |
|
| 200 |
+ v_ignore := false; |
|
| 201 |
+ v_store := false; |
|
| 202 |
+ v_finish := false; |
|
| 203 |
+ -- incoming data |
|
| 204 |
+ IF s_rxframe_data_en = '1' THEN |
|
| 205 |
+ IF r_rx_start = r_rx_end THEN |
|
| 206 |
+ v_ignore := true; -- buffer not available -> ignore rest of packet |
|
| 207 |
+ ELSIF r_rx_cur = r_rx_end THEN |
|
| 208 |
+ v_ignore := true; -- buffer full -> ignore rest of packet |
|
| 209 |
+ ELSIF s_wrbuf_wr_rdy = '0' THEN |
|
| 210 |
+ v_ignore := true; -- bus master write buffer full -> ignore rest of packet |
|
| 211 |
+ ELSE |
|
| 212 |
+ v_store := true; -- store data |
|
| 213 |
+ END IF; |
|
| 214 |
+ -- packet complete |
|
| 157 | 215 |
ELSIF s_rxframe_done = '1' THEN |
| 158 |
- s_rxfifo_wr_data <= X"DDDDDDDD"; |
|
| 216 |
+ IF r_rx_start = r_rx_end THEN |
|
| 217 |
+ v_abort := true; -- buffer not available -> abort |
|
| 218 |
+ ELSIF r_rx_cur = r_rx_end THEN |
|
| 219 |
+ v_abort := true; -- buffer full -> abort |
|
| 220 |
+ ELSIF s_wrbuf_wr_rdy = '0' THEN |
|
| 221 |
+ v_abort := true; -- bus master write buffer full -> abort |
|
| 222 |
+ ELSIF r_rx_size = X"00000000" THEN |
|
| 223 |
+ v_abort := true; -- empty packet -> abort |
|
| 159 | 224 |
ELSE |
| 160 |
- s_rxfifo_wr_data <= s_rxframe_data; |
|
| 225 |
+ v_finish := true; -- finish packet recpetion |
|
| 226 |
+ END IF; |
|
| 227 |
+ -- error |
|
| 228 |
+ ELSIF s_rxframe_err = '1' THEN |
|
| 229 |
+ v_abort := true; -- abort |
|
| 161 | 230 |
END IF; |
| 162 |
- s_rxfifo_wr_en <= s_rxframe_data_en OR s_rxframe_done OR s_rxframe_err; |
|
| 163 |
- END PROCESS p_rx_if2fifo; |
|
| 164 | 231 |
|
| 165 |
- -- so far only for testing |
|
| 166 |
- rx_fifo: e_block_fifo |
|
| 167 |
- GENERIC MAP ( |
|
| 168 |
- addr_width => 9, |
|
| 169 |
- data_width => 32 |
|
| 170 |
- ) |
|
| 171 |
- PORT MAP ( |
|
| 172 |
- rst => rst, |
|
| 173 |
- clk => clk, |
|
| 174 |
- o_wr_rdy => s_rxfifo_wr_rdy, |
|
| 175 |
- i_wr_data => s_rxfifo_wr_data, |
|
| 176 |
- i_wr_en => s_rxfifo_wr_en, |
|
| 177 |
- o_rd_rdy => s_rxfifo_rd_rdy, |
|
| 178 |
- o_rd_data => s_rxfifo_rd_data, |
|
| 179 |
- i_rd_en => s_rxfifo_rd_en |
|
| 180 |
- ); |
|
| 232 |
+ -- perform action selected above |
|
| 233 |
+ -- abort current packet |
|
| 234 |
+ IF v_abort THEN |
|
| 235 |
+ n_rx_cur <= std_logic_vector(unsigned(r_rx_start) + X"00000004"); |
|
| 236 |
+ n_rx_size <= X"00000000"; |
|
| 237 |
+ -- ignore rest of packet |
|
| 238 |
+ -- count size to ensure it is not zero |
|
| 239 |
+ ELSIF v_ignore THEN |
|
| 240 |
+ n_rx_cur <= r_rx_end; |
|
| 241 |
+ n_rx_size <= std_logic_vector(unsigned(r_rx_size) + X"00000004"); |
|
| 242 |
+ -- store data to current address and advance in buffer |
|
| 243 |
+ ELSIF v_store THEN |
|
| 244 |
+ s_wrbuf_wr_data <= r_rx_cur & s_rxframe_data; |
|
| 245 |
+ s_wrbuf_wr_en <= '1'; |
|
| 246 |
+ n_rx_cur <= std_logic_vector(unsigned(r_rx_cur) + X"00000004"); |
|
| 247 |
+ n_rx_size <= std_logic_vector(unsigned(r_rx_size) + X"00000004"); |
|
| 248 |
+ -- store size to start and restart after packet |
|
| 249 |
+ ELSIF v_finish THEN |
|
| 250 |
+ s_wrbuf_wr_data <= r_rx_start & r_rx_size; |
|
| 251 |
+ s_wrbuf_wr_en <= '1'; |
|
| 252 |
+ n_rx_start <= r_rx_cur; |
|
| 253 |
+ n_rx_cur <= std_logic_vector(unsigned(r_rx_cur) + X"00000004"); |
|
| 254 |
+ n_rx_size <= X"00000000"; |
|
| 255 |
+ END IF; |
|
| 181 | 256 |
|
| 182 |
- -- so far only for testing |
|
| 183 |
- s_rxfifo_rd_en <= '1' WHEN i_addr = "01" AND i_rd_en(0) = '1' ELSE '0'; |
|
| 257 |
+ -- use new buffer |
|
| 258 |
+ -- if no action, no data yet and new_en set |
|
| 259 |
+ IF NOT v_abort AND NOT v_ignore AND NOT v_store AND NOT v_finish AND |
|
| 260 |
+ r_rx_size = X"00000000" AND r_rx_new_en = '1' THEN |
|
| 261 |
+ -- terminate old buffer by writing size 0 (if old buffer was available) |
|
| 262 |
+ IF r_rx_start /= r_rx_end THEN |
|
| 263 |
+ s_wrbuf_wr_data <= r_rx_start & X"00000000"; |
|
| 264 |
+ s_wrbuf_wr_en <= '1'; |
|
| 265 |
+ END IF; |
|
| 266 |
+ -- take over new_start and new_end |
|
| 267 |
+ n_rx_start <= r_rx_new_start; |
|
| 268 |
+ n_rx_cur <= std_logic_vector(unsigned(r_rx_new_start) + X"00000004"); |
|
| 269 |
+ n_rx_size <= X"00000000"; |
|
| 270 |
+ n_rx_end <= r_rx_new_end; |
|
| 271 |
+ -- signal overtake of new buffer to process p_write |
|
| 272 |
+ s_rx_new <= '1'; |
|
| 273 |
+ END IF; |
|
| 274 |
+ END PROCESS p_rx_next; |
|
| 184 | 275 |
|
| 185 |
- -- so far only for testing |
|
| 186 |
- p_rx_test_rd: PROCESS (rst, clk) |
|
| 276 |
+ p_rx_sync: PROCESS(rst, clk) |
|
| 187 | 277 |
BEGIN |
| 188 | 278 |
IF rst = '1' THEN |
| 189 |
- o_rd_data <= X"00000000"; |
|
| 279 |
+ r_rx_start <= X"00000000"; |
|
| 280 |
+ r_rx_cur <= X"00000004"; |
|
| 281 |
+ r_rx_size <= X"00000000"; |
|
| 282 |
+ r_rx_end <= X"00000000"; |
|
| 283 |
+ r_rx_new_start <= X"00000000"; |
|
| 284 |
+ r_rx_new_end <= X"00000000"; |
|
| 285 |
+ r_rx_new_en <= '0'; |
|
| 190 | 286 |
ELSIF rising_edge(clk) THEN |
| 191 |
- o_rd_data <= X"00000000"; |
|
| 192 |
- IF i_addr = "00" THEN |
|
| 193 |
- o_rd_data(0) <= s_rxfifo_rd_rdy; |
|
| 194 |
- ELSIF i_addr = "01" THEN |
|
| 195 |
- o_rd_data <= s_rxfifo_rd_data; |
|
| 287 |
+ r_rx_start <= n_rx_start; |
|
| 288 |
+ r_rx_cur <= n_rx_cur; |
|
| 289 |
+ r_rx_size <= n_rx_size; |
|
| 290 |
+ r_rx_end <= n_rx_end; |
|
| 291 |
+ r_rx_new_start <= n_rx_new_start; |
|
| 292 |
+ r_rx_new_end <= n_rx_new_end; |
|
| 293 |
+ r_rx_new_en <= n_rx_new_en; |
|
| 196 | 294 |
END IF; |
| 197 |
- END IF; |
|
| 198 |
- END PROCESS p_rx_test_rd; |
|
| 295 |
+ END PROCESS p_rx_sync; |
|
| 199 | 296 |
|
| 200 |
- pin_o_txd <= "0000"; |
|
| 201 |
- pin_o_tx_en <= '0'; |
|
| 297 |
+ -- register interface write |
|
| 298 |
+ p_write: PROCESS(r_rx_new_start, r_rx_new_end, r_rx_new_en, |
|
| 299 |
+ s_rx_new, |
|
| 300 |
+ i_addr, i_wr_data, i_wr_en) |
|
| 301 |
+ BEGIN |
|
| 302 |
+ n_rx_new_start <= r_rx_new_start; |
|
| 303 |
+ n_rx_new_end <= r_rx_new_end; |
|
| 304 |
+ n_rx_new_en <= r_rx_new_en; |
|
| 305 |
+ IF s_rx_new = '1' THEN |
|
| 306 |
+ n_rx_new_en <= '0'; -- new buffer has been overtaken, reset new_en |
|
| 307 |
+ END IF; |
|
| 308 |
+ IF i_wr_en = "1111" THEN |
|
| 309 |
+ CASE i_addr IS |
|
| 310 |
+ WHEN "100" => n_rx_new_start <= i_wr_data; |
|
| 311 |
+ WHEN "101" => n_rx_new_end <= i_wr_data; |
|
| 312 |
+ WHEN "110" => n_rx_new_en <= i_wr_data(0); |
|
| 313 |
+ WHEN OTHERS => NULL; |
|
| 314 |
+ END CASE; |
|
| 315 |
+ END IF; |
|
| 316 |
+ END PROCESS p_write; |
|
| 202 | 317 |
|
| 203 |
- -- bus master: bullshit for now |
|
| 204 |
- p_bm: PROCESS(rst, clk) |
|
| 318 |
+ -- register interface read |
|
| 319 |
+ p_read: PROCESS(rst, clk) |
|
| 205 | 320 |
BEGIN |
| 206 | 321 |
IF rst = '1' THEN |
| 207 |
- r_cnt <= 0; |
|
| 322 |
+ o_rd_data <= (OTHERS => '0'); |
|
| 208 | 323 |
ELSIF rising_edge(clk) THEN |
| 209 |
- IF r_cnt < 3 THEN |
|
| 210 |
- r_cnt <= r_cnt + 1; |
|
| 211 |
- ELSE |
|
| 212 |
- r_cnt <= 0; |
|
| 324 |
+ o_rd_data <= (OTHERS => '0'); |
|
| 325 |
+ CASE i_addr IS |
|
| 326 |
+ WHEN "000" => o_rd_data <= r_rx_start; |
|
| 327 |
+ WHEN "001" => o_rd_data <= r_rx_cur; |
|
| 328 |
+ WHEN "010" => o_rd_data <= r_rx_size; |
|
| 329 |
+ WHEN "011" => o_rd_data <= r_rx_end; |
|
| 330 |
+ WHEN "100" => o_rd_data <= r_rx_new_start; |
|
| 331 |
+ WHEN "101" => o_rd_data <= r_rx_new_end; |
|
| 332 |
+ WHEN "110" => o_rd_data(0) <= r_rx_new_en; |
|
| 333 |
+ WHEN OTHERS => NULL; |
|
| 334 |
+ END CASE; |
|
| 213 | 335 |
END IF; |
| 214 |
- END IF; |
|
| 215 |
- END PROCESS p_bm; |
|
| 336 |
+ END PROCESS p_read; |
|
| 337 |
+ |
|
| 338 |
+ -- bus master write buffer |
|
| 339 |
+ -- as the core has lower bus priority than ethernet, |
|
| 340 |
+ -- the core will never access memory or ethernet registers |
|
| 341 |
+ -- when data is in this buffer |
|
| 342 |
+ wrbuf: e_block_fifo |
|
| 343 |
+ GENERIC MAP ( |
|
| 344 |
+ addr_width => 2, |
|
| 345 |
+ data_width => 64 |
|
| 346 |
+ ) |
|
| 347 |
+ PORT MAP ( |
|
| 348 |
+ rst => rst, |
|
| 349 |
+ clk => clk, |
|
| 350 |
+ o_wr_rdy => s_wrbuf_wr_rdy, |
|
| 351 |
+ i_wr_data => s_wrbuf_wr_data, |
|
| 352 |
+ i_wr_en => s_wrbuf_wr_en, |
|
| 353 |
+ o_rd_rdy => s_wrbuf_rd_rdy, |
|
| 354 |
+ o_rd_data => s_wrbuf_rd_data, |
|
| 355 |
+ i_rd_en => s_wrbuf_rd_en |
|
| 356 |
+ ); |
|
| 216 | 357 |
|
| 217 |
- -- bus master: bullshit for now |
|
| 218 |
- o_bm_req <= '1' WHEN r_cnt = 0 ELSE '0'; |
|
| 358 |
+ pin_o_txd <= "0000"; |
|
| 359 |
+ pin_o_tx_en <= '0'; |
|
| 360 |
+ |
|
| 361 |
+ -- bus master write |
|
| 362 |
+ p_bm_wr: PROCESS(s_wrbuf_rd_rdy, s_wrbuf_rd_data, i_bm_grant) |
|
| 363 |
+ BEGIN |
|
| 364 |
+ s_wrbuf_rd_en <= '0'; |
|
| 365 |
+ o_bm_req <= '0'; |
|
| 219 | 366 |
o_bm_addr <= (OTHERS => '0'); |
| 220 | 367 |
o_bm_rd_en <= (OTHERS => '0'); |
| 221 | 368 |
o_bm_wr_data <= (OTHERS => '0'); |
| 222 | 369 |
o_bm_wr_en <= (OTHERS => '0'); |
| 370 |
+ -- process write requests from write buffer |
|
| 371 |
+ IF s_wrbuf_rd_rdy = '1' THEN |
|
| 372 |
+ s_wrbuf_rd_en <= i_bm_grant; |
|
| 373 |
+ o_bm_req <= '1'; |
|
| 374 |
+ o_bm_addr <= s_wrbuf_rd_data(63 DOWNTO 32); |
|
| 375 |
+ o_bm_wr_data <= s_wrbuf_rd_data(31 DOWNTO 0); |
|
| 376 |
+ o_bm_wr_en <= "1111"; |
|
| 377 |
+ END IF; |
|
| 378 |
+ END PROCESS p_bm_wr; |
|
| 223 | 379 |
|
| 224 | 380 |
END ARCHITECTURE a_io_eth; |
| 225 | 381 |
|
| ... | ... |
@@ -70,7 +70,8 @@ BEGIN |
| 70 | 70 |
); |
| 71 | 71 |
|
| 72 | 72 |
p_next: PROCESS(r_state, r_mac_cnt, r_data_cnt, r_out_data, |
| 73 |
- i_data, i_data_en, i_done, i_err, i_mac) |
|
| 73 |
+ i_data, i_data_en, i_done, i_err, i_mac, |
|
| 74 |
+ s_crc_crc) |
|
| 74 | 75 |
VARIABLE v_mac: std_logic_vector(7 DOWNTO 0); |
| 75 | 76 |
VARIABLE v_data: boolean; |
| 76 | 77 |
BEGIN |
| ... | ... |
@@ -16,7 +16,7 @@ |
| 16 | 16 |
|
| 17 | 17 |
<files> |
| 18 | 18 |
<file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL"> |
| 19 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
|
| 19 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
|
| 20 | 20 |
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> |
| 21 | 21 |
</file> |
| 22 | 22 |
<file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL"> |
| ... | ... |
@@ -24,15 +24,15 @@ |
| 24 | 24 |
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> |
| 25 | 25 |
</file> |
| 26 | 26 |
<file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL"> |
| 27 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
|
| 27 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> |
|
| 28 | 28 |
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> |
| 29 | 29 |
</file> |
| 30 | 30 |
<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL"> |
| 31 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> |
|
| 31 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> |
|
| 32 | 32 |
<association xil_pn:name="Implementation" xil_pn:seqID="17"/> |
| 33 | 33 |
</file> |
| 34 | 34 |
<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL"> |
| 35 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
|
| 35 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
|
| 36 | 36 |
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> |
| 37 | 37 |
</file> |
| 38 | 38 |
<file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL"> |
| ... | ... |
@@ -40,33 +40,33 @@ |
| 40 | 40 |
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> |
| 41 | 41 |
</file> |
| 42 | 42 |
<file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL"> |
| 43 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> |
|
| 43 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> |
|
| 44 | 44 |
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> |
| 45 | 45 |
</file> |
| 46 | 46 |
<file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL"> |
| 47 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
|
| 47 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> |
|
| 48 | 48 |
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> |
| 49 | 49 |
</file> |
| 50 | 50 |
<file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL"> |
| 51 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> |
|
| 51 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> |
|
| 52 | 52 |
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> |
| 53 | 53 |
</file> |
| 54 | 54 |
<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL"> |
| 55 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> |
|
| 55 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/> |
|
| 56 | 56 |
<association xil_pn:name="Implementation" xil_pn:seqID="29"/> |
| 57 | 57 |
</file> |
| 58 | 58 |
<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL"> |
| 59 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> |
|
| 59 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/> |
|
| 60 | 60 |
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/> |
| 61 | 61 |
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/> |
| 62 | 62 |
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/> |
| 63 | 63 |
</file> |
| 64 | 64 |
<file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL"> |
| 65 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> |
|
| 65 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> |
|
| 66 | 66 |
<association xil_pn:name="Implementation" xil_pn:seqID="24"/> |
| 67 | 67 |
</file> |
| 68 | 68 |
<file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL"> |
| 69 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> |
|
| 69 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> |
|
| 70 | 70 |
<association xil_pn:name="Implementation" xil_pn:seqID="20"/> |
| 71 | 71 |
</file> |
| 72 | 72 |
<file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF"> |
| ... | ... |
@@ -76,56 +76,56 @@ |
| 76 | 76 |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
| 77 | 77 |
</file> |
| 78 | 78 |
<file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL"> |
| 79 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> |
|
| 79 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> |
|
| 80 | 80 |
<association xil_pn:name="Implementation" xil_pn:seqID="23"/> |
| 81 | 81 |
</file> |
| 82 | 82 |
<file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL"> |
| 83 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> |
|
| 83 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> |
|
| 84 | 84 |
<association xil_pn:name="Implementation" xil_pn:seqID="21"/> |
| 85 | 85 |
</file> |
| 86 | 86 |
<file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL"> |
| 87 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> |
|
| 87 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> |
|
| 88 | 88 |
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> |
| 89 | 89 |
</file> |
| 90 | 90 |
<file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF"> |
| 91 | 91 |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
| 92 | 92 |
</file> |
| 93 | 93 |
<file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL"> |
| 94 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> |
|
| 94 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> |
|
| 95 | 95 |
<association xil_pn:name="Implementation" xil_pn:seqID="28"/> |
| 96 | 96 |
</file> |
| 97 | 97 |
<file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL"> |
| 98 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> |
|
| 98 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> |
|
| 99 | 99 |
<association xil_pn:name="Implementation" xil_pn:seqID="27"/> |
| 100 | 100 |
</file> |
| 101 | 101 |
<file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL"> |
| 102 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> |
|
| 102 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> |
|
| 103 | 103 |
<association xil_pn:name="Implementation" xil_pn:seqID="26"/> |
| 104 | 104 |
</file> |
| 105 | 105 |
<file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL"> |
| 106 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> |
|
| 106 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> |
|
| 107 | 107 |
<association xil_pn:name="Implementation" xil_pn:seqID="25"/> |
| 108 | 108 |
</file> |
| 109 | 109 |
<file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL"> |
| 110 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> |
|
| 110 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> |
|
| 111 | 111 |
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> |
| 112 | 112 |
</file> |
| 113 | 113 |
<file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL"> |
| 114 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> |
|
| 114 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> |
|
| 115 | 115 |
<association xil_pn:name="Implementation" xil_pn:seqID="19"/> |
| 116 | 116 |
</file> |
| 117 | 117 |
<file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF"> |
| 118 | 118 |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
| 119 | 119 |
</file> |
| 120 | 120 |
<file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL"> |
| 121 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> |
|
| 121 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> |
|
| 122 | 122 |
<association xil_pn:name="Implementation" xil_pn:seqID="18"/> |
| 123 | 123 |
</file> |
| 124 | 124 |
<file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF"> |
| 125 | 125 |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
| 126 | 126 |
</file> |
| 127 | 127 |
<file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL"> |
| 128 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> |
|
| 128 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> |
|
| 129 | 129 |
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> |
| 130 | 130 |
</file> |
| 131 | 131 |
<file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL"> |
| ... | ... |
@@ -133,26 +133,26 @@ |
| 133 | 133 |
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> |
| 134 | 134 |
</file> |
| 135 | 135 |
<file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL"> |
| 136 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> |
|
| 136 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> |
|
| 137 | 137 |
<association xil_pn:name="Implementation" xil_pn:seqID="22"/> |
| 138 | 138 |
</file> |
| 139 | 139 |
<file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL"> |
| 140 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> |
|
| 140 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> |
|
| 141 | 141 |
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> |
| 142 | 142 |
</file> |
| 143 | 143 |
<file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL"> |
| 144 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> |
|
| 144 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> |
|
| 145 | 145 |
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> |
| 146 | 146 |
</file> |
| 147 | 147 |
<file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF"> |
| 148 | 148 |
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> |
| 149 | 149 |
</file> |
| 150 | 150 |
<file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL"> |
| 151 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> |
|
| 151 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> |
|
| 152 | 152 |
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> |
| 153 | 153 |
</file> |
| 154 | 154 |
<file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL"> |
| 155 |
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="202"/> |
|
| 155 |
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> |
|
| 156 | 156 |
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> |
| 157 | 157 |
</file> |
| 158 | 158 |
</files> |
| ... | ... |
@@ -273,7 +273,7 @@ |
| 273 | 273 |
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
| 274 | 274 |
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
| 275 | 275 |
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> |
| 276 |
- <property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/> |
|
| 276 |
+ <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> |
|
| 277 | 277 |
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
| 278 | 278 |
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> |
| 279 | 279 |
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> |
| ... | ... |
@@ -332,7 +332,7 @@ |
| 332 | 332 |
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> |
| 333 | 333 |
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> |
| 334 | 334 |
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/> |
| 335 |
- <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> |
|
| 335 |
+ <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="Standard" xil_pn:valueState="non-default"/> |
|
| 336 | 336 |
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> |
| 337 | 337 |
<property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/> |
| 338 | 338 |
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> |
| ... | ... |
@@ -0,0 +1 @@ |
| 1 |
+55 55 55 55 55 55 55 D5 FF FF FF FF FF FF 00 1D 60 DC 75 2D 08 00 45 00 00 36 39 DE 40 00 40 11 40 27 C0 A8 00 0A FF FF FF FF 97 53 00 01 00 22 9B D1 44 69 65 73 20 69 73 74 20 65 69 6E 20 6C 61 6E 67 65 72 20 54 65 73 74 21 0A AB 83 8D 1D |
| ... | ... |
@@ -0,0 +1 @@ |
| 1 |
+X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"D", X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"0", X"0", X"D", X"1", X"0", X"6", X"C", X"D", X"5", X"7", X"D", X"2", X"8", X"0", X"0", X"0", X"5", X"4", X"0", X"0", X"0", X"0", X"6", X"3", X"9", X"3", X"E", X"D", X"0", X"4", X"0", X"0", X"0", X"4", X"1", X"1", X"0", X"4", X"7", X"2", X"0", X"C", X"8", X"A", X"0", X"0", X"A", X"0", X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"7", X"9", X"3", X"5", X"0", X"0", X"1", X"0", X"0", X"0", X"2", X"2", X"B", X"9", X"1", X"D", X"4", X"4", X"9", X"6", X"5", X"6", X"3", X"7", X"0", X"2", X"9", X"6", X"3", X"7", X"4", X"7", X"0", X"2", X"5", X"6", X"9", X"6", X"E", X"6", X"0", X"2", X"C", X"6", X"1", X"6", X"E", X"6", X"7", X"6", X"5", X"6", X"2", X"7", X"0", X"2", X"4", X"5", X"5", X"6", X"3", X"7", X"4", X"7", X"1", X"2", X"A", X"0", X"B", X"A", X"3", X"8", X"D", X"8", X"D", X"1", |
| ... | ... |
@@ -74,7 +74,7 @@ ARCHITECTURE a_system OF e_system IS |
| 74 | 74 |
SIGNAL s_uart_rd_en: std_logic_vector( 3 DOWNTO 0); |
| 75 | 75 |
SIGNAL s_uart_wr_data: std_logic_vector(31 DOWNTO 0); |
| 76 | 76 |
SIGNAL s_uart_wr_en: std_logic_vector( 3 DOWNTO 0); |
| 77 |
- SIGNAL s_eth_addr: std_logic_vector( 3 DOWNTO 0); |
|
| 77 |
+ SIGNAL s_eth_addr: std_logic_vector( 4 DOWNTO 0); |
|
| 78 | 78 |
SIGNAL s_eth_rd_data: std_logic_vector(31 DOWNTO 0); |
| 79 | 79 |
SIGNAL s_eth_rd_en: std_logic_vector( 3 DOWNTO 0); |
| 80 | 80 |
SIGNAL s_eth_wr_data: std_logic_vector(31 DOWNTO 0); |
| ... | ... |
@@ -212,7 +212,7 @@ ARCHITECTURE a_system OF e_system IS |
| 212 | 212 |
PORT ( |
| 213 | 213 |
rst: IN std_logic; |
| 214 | 214 |
clk: IN std_logic; |
| 215 |
- i_addr: IN std_logic_vector( 1 DOWNTO 0); |
|
| 215 |
+ i_addr: IN std_logic_vector( 2 DOWNTO 0); |
|
| 216 | 216 |
o_rd_data: OUT std_logic_vector(31 DOWNTO 0); |
| 217 | 217 |
i_rd_en: IN std_logic_vector( 3 DOWNTO 0); |
| 218 | 218 |
i_wr_data: IN std_logic_vector(31 DOWNTO 0); |
| ... | ... |
@@ -393,7 +393,7 @@ BEGIN |
| 393 | 393 |
s_uart_wr_data <= s_dbus_wr_data; |
| 394 | 394 |
s_uart_wr_en <= s_dbus_wr_en; |
| 395 | 395 |
WHEN X"04" => |
| 396 |
- s_eth_addr <= s_dbus_addr(3 DOWNTO 0); |
|
| 396 |
+ s_eth_addr <= s_dbus_addr(4 DOWNTO 0); |
|
| 397 | 397 |
s_eth_rd_en <= s_dbus_rd_en; |
| 398 | 398 |
s_eth_wr_data <= s_dbus_wr_data; |
| 399 | 399 |
s_eth_wr_en <= s_dbus_wr_en; |
| ... | ... |
@@ -499,7 +499,7 @@ BEGIN |
| 499 | 499 |
PORT MAP ( |
| 500 | 500 |
rst => rst, |
| 501 | 501 |
clk => clk, |
| 502 |
- i_addr => s_eth_addr(3 DOWNTO 2), |
|
| 502 |
+ i_addr => s_eth_addr(4 DOWNTO 2), |
|
| 503 | 503 |
o_rd_data => s_eth_rd_data, |
| 504 | 504 |
i_rd_en => s_eth_rd_en, |
| 505 | 505 |
i_wr_data => s_eth_wr_data, |
| 506 | 506 |