show more eth signals
Stefan Schuermans commited on 2012-03-20 22:09:21
Showing 2 changed files, with 17 additions and 2 deletions.
- Default.wcfg 7598872..d72252b
- mips_sys.xise 298593e..62edd47
| ... | ... |
@@ -15,7 +15,7 @@ |
| 15 | 15 |
</top_modules> |
| 16 | 16 |
</db_ref> |
| 17 | 17 |
</db_ref_list> |
| 18 |
- <WVObjectSize size="19" /> |
|
| 18 |
+ <WVObjectSize size="22" /> |
|
| 19 | 19 |
<wvobject fp_name="/e_testbed/s_clk" type="logic" db_ref_id="1"> |
| 20 | 20 |
<obj_property name="ElementShortName">s_clk</obj_property> |
| 21 | 21 |
<obj_property name="ObjectShortName">s_clk</obj_property> |
| ... | ... |
@@ -104,4 +104,19 @@ |
| 104 | 104 |
<obj_property name="ObjectShortName">r_rx_new_end[31:0]</obj_property> |
| 105 | 105 |
<obj_property name="Radix">HEXRADIX</obj_property> |
| 106 | 106 |
</wvobject> |
| 107 |
+ <wvobject fp_name="/e_testbed/system/eth/r_tx_end" type="array" db_ref_id="1"> |
|
| 108 |
+ <obj_property name="ElementShortName">r_tx_end[31:0]</obj_property> |
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| 109 |
+ <obj_property name="ObjectShortName">r_tx_end[31:0]</obj_property> |
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| 110 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 111 |
+ </wvobject> |
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| 112 |
+ <wvobject fp_name="/e_testbed/system/eth/r_tx_start" type="array" db_ref_id="1"> |
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| 113 |
+ <obj_property name="ElementShortName">r_tx_start[31:0]</obj_property> |
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+ <obj_property name="ObjectShortName">r_tx_start[31:0]</obj_property> |
|
| 115 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 116 |
+ </wvobject> |
|
| 117 |
+ <wvobject fp_name="/e_testbed/system/eth/r_tx_pos" type="array" db_ref_id="1"> |
|
| 118 |
+ <obj_property name="ElementShortName">r_tx_pos[31:0]</obj_property> |
|
| 119 |
+ <obj_property name="ObjectShortName">r_tx_pos[31:0]</obj_property> |
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| 120 |
+ <obj_property name="Radix">HEXRADIX</obj_property> |
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| 121 |
+ </wvobject> |
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| 107 | 122 |
</wave_config> |
| ... | ... |
@@ -407,7 +407,7 @@ |
| 407 | 407 |
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> |
| 408 | 408 |
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> |
| 409 | 409 |
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> |
| 410 |
- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="30 ms" xil_pn:valueState="non-default"/> |
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| 410 |
+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="40 ms" xil_pn:valueState="non-default"/> |
|
| 411 | 411 |
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
| 412 | 412 |
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
| 413 | 413 |
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> |
| 414 | 414 |