implemented ethernet RX CRC check (e4ce80e) - mips_sys · BlinkenArea

implemented ethernet RX CRC check

Stefan Schuermans commited on 2012-03-03 17:09:36
Showing 2 changed files, with 69 additions and 26 deletions.

io/eth/rxframe.vhd 4583867..6b0191b
mips_sys.xise 2cb3e85..8698316

io/eth/rxframe.vhd

@@ -41,8 +41,34 @@ ARCHITECTURE a_io_eth_rxframe OF e_io_eth_rxframe IS
     SIGNAL r_out_err:     std_logic                     := '0';
     SIGNAL n_out_err:     std_logic;
 
+    SIGNAL s_crc_en:    std_logic;
+    SIGNAL s_crc_start: std_logic;
+    SIGNAL s_crc_data:  std_logic_vector( 7 DOWNTO 0);
+    SIGNAL s_crc_crc:   std_logic_vector(31 DOWNTO 0);
+
+    COMPONENT e_block_crc32 IS
+        PORT (
+            rst:     IN  std_logic;
+            clk:     IN  std_logic;
+            i_en:    IN  std_logic;
+            i_start: IN  std_logic;
+            i_data:  IN  std_logic_vector( 7 DOWNTO 0);
+            o_crc:   OUT std_logic_vector(31 DOWNTO 0)
+        );
+    END COMPONENT e_block_crc32;
+
 BEGIN
 
+    crc32: e_block_crc32
+        PORT MAP (
+            rst     => rst,
+            clk     => clk,
+            i_en    => s_crc_en,
+            i_start => s_crc_start,
+            i_data  => s_crc_data,
+            o_crc   => s_crc_crc
+        );
+
     p_next: PROCESS(r_state, r_mac_cnt, r_data_cnt, r_out_data,
                     i_data, i_data_en, i_done, i_err, i_mac)
         VARIABLE v_mac:  std_logic_vector(7 DOWNTO 0);
@@ -55,6 +81,10 @@ BEGIN
         n_out_data_en <= '0';
         n_out_done    <= '0';
         n_out_err     <= '0';
+        s_crc_en    <= '0';
+        s_crc_start <= '0';
+        s_crc_data  <= (OTHERS => '0');
+        -- next state
         v_data := false;
         CASE r_state IS
             WHEN st_idle =>
@@ -144,13 +174,19 @@ BEGIN
                     v_data  := true;
                 ELSIF i_done = '1' THEN
                     n_state    <= st_idle;
+                    -- check CRC: last 4 bytes = 4 byte delayed CRC value
+                    IF r_out_data = s_crc_crc THEN
                         n_out_done <= '1';
+                    ELSE
+                        n_out_err <= '1';
+                    END IF;
                 ELSIF i_err = '1' THEN
                     n_state   <= st_idle;
                     n_out_err <= '1';
                 END IF;
             WHEN OTHERS => NULL;
         END CASE;
+        -- data output / CRC
         IF v_data THEN
             n_out_data(31 DOWNTO 24) <= i_data;
             n_out_data(23 DOWNTO  0) <= r_out_data(31 DOWNTO 8);
@@ -160,6 +196,13 @@ BEGIN
                 n_data_cnt    <= 0;
                 n_out_data_en <= '1';
             END IF;
+            -- calculate CRC with 4 bytes delay,
+            -- so CRC value is available when i_done = 1
+            s_crc_en   <= '1';
+            s_crc_data <= r_out_data(7 DOWNTO 0);
+            IF r_mac_cnt = 4 THEN
+                s_crc_start <= '1';
+            END IF;
         END IF;
     END PROCESS p_next;
 

mips_sys.xise

View file @ e4ce80e

@@ -17,7 +17,7 @@
   <files>
     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
@@ -25,15 +25,15 @@
     </file>
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
@@ -41,19 +41,19 @@
     </file>
     <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
     </file>
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
@@ -63,11 +63,11 @@
     </file>
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -77,56 +77,56 @@
     </file>
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
     </file>
     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
@@ -134,26 +134,26 @@
     </file>
     <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="202"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
   </files>
 


...	...	@@ -41,8 +41,34 @@ ARCHITECTURE a_io_eth_rxframe OF e_io_eth_rxframe IS
41	41	SIGNAL r_out_err: std_logic := '0';
42	42	SIGNAL n_out_err: std_logic;
43	43
	44	+ SIGNAL s_crc_en: std_logic;
	45	+ SIGNAL s_crc_start: std_logic;
	46	+ SIGNAL s_crc_data: std_logic_vector( 7 DOWNTO 0);
	47	+ SIGNAL s_crc_crc: std_logic_vector(31 DOWNTO 0);
	48	+
	49	+ COMPONENT e_block_crc32 IS
	50	+ PORT (
	51	+ rst: IN std_logic;
	52	+ clk: IN std_logic;
	53	+ i_en: IN std_logic;
	54	+ i_start: IN std_logic;
	55	+ i_data: IN std_logic_vector( 7 DOWNTO 0);
	56	+ o_crc: OUT std_logic_vector(31 DOWNTO 0)
	57	+ );
	58	+ END COMPONENT e_block_crc32;
	59	+
44	60	BEGIN
45	61
	62	+ crc32: e_block_crc32
	63	+ PORT MAP (
	64	+ rst => rst,
	65	+ clk => clk,
	66	+ i_en => s_crc_en,
	67	+ i_start => s_crc_start,
	68	+ i_data => s_crc_data,
	69	+ o_crc => s_crc_crc
	70	+ );
	71	+
46	72	p_next: PROCESS(r_state, r_mac_cnt, r_data_cnt, r_out_data,
47	73	i_data, i_data_en, i_done, i_err, i_mac)
48	74	VARIABLE v_mac: std_logic_vector(7 DOWNTO 0);
...	...	@@ -55,6 +81,10 @@ BEGIN
55	81	n_out_data_en <= '0';
56	82	n_out_done <= '0';
57	83	n_out_err <= '0';
	84	+ s_crc_en <= '0';
	85	+ s_crc_start <= '0';
	86	+ s_crc_data <= (OTHERS => '0');
	87	+ -- next state
58	88	v_data := false;
59	89	CASE r_state IS
60	90	WHEN st_idle =>
...	...	@@ -144,13 +174,19 @@ BEGIN
144	174	v_data := true;
145	175	ELSIF i_done = '1' THEN
146	176	n_state <= st_idle;
	177	+ -- check CRC: last 4 bytes = 4 byte delayed CRC value
	178	+ IF r_out_data = s_crc_crc THEN
147	179	n_out_done <= '1';
	180	+ ELSE
	181	+ n_out_err <= '1';
	182	+ END IF;
148	183	ELSIF i_err = '1' THEN
149	184	n_state <= st_idle;
150	185	n_out_err <= '1';
151	186	END IF;
152	187	WHEN OTHERS => NULL;
153	188	END CASE;
	189	+ -- data output / CRC
154	190	IF v_data THEN
155	191	n_out_data(31 DOWNTO 24) <= i_data;
156	192	n_out_data(23 DOWNTO 0) <= r_out_data(31 DOWNTO 8);
...	...	@@ -160,6 +196,13 @@ BEGIN
160	196	n_data_cnt <= 0;
161	197	n_out_data_en <= '1';
162	198	END IF;
	199	+ -- calculate CRC with 4 bytes delay,
	200	+ -- so CRC value is available when i_done = 1
	201	+ s_crc_en <= '1';
	202	+ s_crc_data <= r_out_data(7 DOWNTO 0);
	203	+ IF r_mac_cnt = 4 THEN
	204	+ s_crc_start <= '1';
	205	+ END IF;
163	206	END IF;
164	207	END PROCESS p_next;
165	208

...	...	@@ -17,7 +17,7 @@
17	17	<files>
18	18	<file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19	19	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
20		- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
	20	+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
21	21	</file>
22	22	<file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
23	23	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
...	...	@@ -25,15 +25,15 @@
25	25	</file>
26	26	<file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27	27	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
28		- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
	28	+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31	31	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
32		- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
	32	+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
33	33	</file>
34	34	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35	35	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
36		- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
	36	+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
37	37	</file>
38	38	<file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
39	39	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
...	...	@@ -41,19 +41,19 @@
41	41	</file>
42	42	<file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
43	43	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
44		- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
	44	+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
45	45	</file>
46	46	<file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
47	47	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
48		- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
	48	+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
49	49	</file>
50	50	<file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
51	51	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
52		- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
	52	+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
53	53	</file>
54	54	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55	55	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
56		- <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
	56	+ <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
57	57	</file>
58	58	<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59	59	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
...	...	@@ -63,11 +63,11 @@
63	63	</file>
64	64	<file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65	65	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
66		- <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
	66	+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
67	67	</file>
68	68	<file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69	69	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
70		- <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
	70	+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
71	71	</file>
72	72	<file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
73	73	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...	...	@@ -77,56 +77,56 @@
77	77	</file>
78	78	<file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
79	79	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
80		- <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
	80	+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
81	81	</file>
82	82	<file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
83	83	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
84		- <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
	84	+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
85	85	</file>
86	86	<file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
87	87	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
88		- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
	88	+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
89	89	</file>
90	90	<file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
91	91	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
92	92	</file>
93	93	<file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
94	94	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
95		- <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
	95	+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
96	96	</file>
97	97	<file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
98	98	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
99		- <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
	99	+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
100	100	</file>
101	101	<file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
102	102	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
103		- <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
	103	+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
104	104	</file>
105	105	<file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
106	106	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
107		- <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
	107	+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
108	108	</file>
109	109	<file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
110	110	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
111		- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
	111	+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
112	112	</file>
113	113	<file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
114	114	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
115		- <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
	115	+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
116	116	</file>
117	117	<file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118	118	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119	119	</file>
120	120	<file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
121	121	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
122		- <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
	122	+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
123	123	</file>
124	124	<file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
125	125	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
126	126	</file>
127	127	<file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
128	128	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
129		- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
	129	+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
130	130	</file>
131	131	<file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
132	132	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
...	...	@@ -134,26 +134,26 @@
134	134	</file>
135	135	<file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
136	136	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
137		- <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
	137	+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
138	138	</file>
139	139	<file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
140	140	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
141		- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
	141	+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
142	142	</file>
143	143	<file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
144	144	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
145		- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
	145	+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
146	146	</file>
147	147	<file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
148	148	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
149	149	</file>
150	150	<file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL">
151	151	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
152		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	152	+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
153	153	</file>
154	154	<file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
155	155	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="202"/>
156		- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
	156	+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
157	157	</file>
158	158	</files>
159	159
160	160