mips_sys

@@ -7,6 +7,17 @@ static unsigned int eth_idx_hw;

 static unsigned int eth_rx_buf[2][256];

 static unsigned int *eth_rx_pos;

+/**

+ * @brief set MAC address

+ * @param[in] mac MAC address

+ */

+static void eth_mac_set(const unsigned char mac[6])

+{

+  unsigned int i;

+  for (i = 0; i < 6; ++i)

+    ((volatile unsigned char *)(eth_ptr + 12))[i] = mac[i];

+}

+

 /**

  * @brief provide new receive buffer

  * @param[in] ptr pointer to new receive buffer

@@ -31,6 +42,13 @@ static void * eth_rx_get_pos(void)

   return (void *)eth_ptr[0];

 }

+/** initialize MAC address */

+void eth_mac_init(void)

+{

+  static const unsigned char mac[6] = {0x02, 0x03, 0x04, 0x05, 0x06, 0x07};

+  eth_mac_set(mac);

+}

+

 /** initialize receiver */

 void eth_rx_init(void)

 {

@@ -1,6 +1,9 @@

 #ifndef ETH_H

 #define ETH_H

+/** initialize MAC address */

+void eth_mac_init(void);

+

 /** initialize receiver */

 void eth_rx_init(void);

@@ -110,6 +110,7 @@ int main()

   leds_set_state(0x02);

 #ifdef CFG_ETH_RX

+  eth_mac_init();

   eth_rx_init();

 #endif

@@ -100,6 +100,10 @@ ARCHITECTURE a_io_eth OF e_io_eth IS

     SIGNAL r_tx_en:    std_logic                     := '0';

     SIGNAL n_tx_en:    std_logic;

+    -- MAC address register

+    SIGNAL r_mac: std_logic_vector(47 DOWNTO 0) := X"FFFFFFFFFFFF";

+    SIGNAL n_mac: std_logic_vector(47 DOWNTO 0);

+

     -- TX busmaster read state machine

     SIGNAL r_tx_pos:  std_logic_vector(31 DOWNTO 0) := X"00000000";

     SIGNAL n_tx_pos:  std_logic_vector(31 DOWNTO 0);

@@ -233,7 +237,7 @@ BEGIN

             i_data_en => s_rxif_data_en,

             i_done    => s_rxif_done,

             i_err     => s_rxif_err,

-            i_mac     => X"070605040302",

+            i_mac     => r_mac,

             o_data    => s_rxframe_data,

             o_data_en => s_rxframe_data_en,

             o_done    => s_rxframe_done,

@@ -391,6 +395,7 @@ BEGIN

             r_tx_start     <= X"00000000";

             r_tx_end       <= X"00000000";

             r_tx_en        <= '0';

+            r_mac          <= X"FFFFFFFFFFFF";

         ELSIF rising_edge(clk) THEN

             r_rx_start     <= n_rx_start;

             r_rx_cur       <= n_rx_cur;

@@ -402,12 +407,13 @@ BEGIN

             r_tx_start     <= n_tx_start;

             r_tx_end       <= n_tx_end;

             r_tx_en        <= n_tx_en;

+            r_mac          <= n_mac;

         END IF;

     END PROCESS p_reg_sync;

     -- register interface write

     p_write: PROCESS(r_rx_new_start, r_rx_new_end, r_rx_new_en, s_rx_new,

-                     r_tx_start, r_tx_end, r_tx_en, s_txframe_done,

+                     r_tx_start, r_tx_end, r_tx_en, s_txframe_done, r_mac,

                      i_addr, i_wr_data, i_wr_en)

     BEGIN

         n_rx_new_start <= r_rx_new_start;

@@ -416,6 +422,7 @@ BEGIN

         n_tx_start     <= r_tx_start;

         n_tx_end       <= r_tx_end;

         n_tx_en        <= r_tx_en;

+        n_mac          <= r_mac;

         s_txframe_en   <= '0';

         IF s_rx_new = '1' THEN

             n_rx_new_en <= '0'; -- new buffer has been overtaken, reset rx_new_en

@@ -423,28 +430,56 @@ BEGIN

         IF s_txframe_done = '1' THEN

             n_tx_en <= '0'; -- TX operation completed, reset tx_en

         END IF;

-        IF i_wr_en = "1111" THEN

         CASE i_addr IS

-                WHEN "0100" => n_rx_new_start <= i_wr_data;

-                WHEN "0101" => n_rx_new_end   <= i_wr_data;

-                WHEN "0110" => IF i_wr_data(0) = '1' THEN

+            WHEN "0100" =>

+                IF i_wr_en = "1111" THEN

+                    n_rx_new_start <= i_wr_data;

+                END IF;

+            WHEN "0101" =>

+                IF i_wr_en = "1111" THEN

+                    n_rx_new_end <= i_wr_data;

+                END IF;

+            WHEN "0110" =>

+                IF i_wr_en(0) = '1' AND i_wr_data(0) = '1' THEN

                     n_rx_new_en <= '1';

                 END IF;

-                WHEN "1000" => IF r_tx_en = '0' THEN

+            WHEN "1000" =>

+                IF i_wr_en = "1111" AND r_tx_en = '0' THEN

                     n_tx_start <= i_wr_data;

                 END IF;

-                WHEN "1001" => IF r_tx_en = '0' THEN

+            WHEN "1001" =>

+                IF i_wr_en = "1111" AND r_tx_en = '0' THEN

                     n_tx_end <= i_wr_data;

                 END IF;

-                WHEN "1010" => IF i_wr_data(0) = '1' THEN

+            WHEN "1010" =>

+                IF i_wr_en(0) = '1' AND i_wr_data(0) = '1' THEN

                     IF r_tx_en = '0' THEN

                         s_txframe_en <= '1';

                     END IF;

                     n_tx_en <= '1';

                 END IF;

+            WHEN "1100" =>

+                IF i_wr_en(0) = '1' THEN

+                    n_mac(7 DOWNTO 0) <= i_wr_data(7 DOWNTO 0);

+                END IF;

+                IF i_wr_en(1) = '1' THEN

+                    n_mac(15 DOWNTO 8) <= i_wr_data(15 DOWNTO 8);

+                END IF;

+                IF i_wr_en(2) = '1' THEN

+                    n_mac(23 DOWNTO 16) <= i_wr_data(23 DOWNTO 16);

+                END IF;

+                IF i_wr_en(3) = '1' THEN

+                    n_mac(31 DOWNTO 24) <= i_wr_data(31 DOWNTO 24);

+                END IF;

+            WHEN "1101" =>

+                IF i_wr_en(0) = '1' THEN

+                    n_mac(39 DOWNTO 32) <= i_wr_data(7 DOWNTO 0);

+                END IF;

+                IF i_wr_en(1) = '1' THEN

+                    n_mac(47 DOWNTO 40) <= i_wr_data(15 DOWNTO 8);

+                END IF;

             WHEN OTHERS => NULL;

         END CASE;

-        END IF;

     END PROCESS p_write;

     -- register interface read

@@ -465,6 +500,8 @@ BEGIN

                 WHEN "1000" => o_rd_data              <= r_tx_start;

                 WHEN "1001" => o_rd_data              <= r_tx_end;

                 WHEN "1010" => o_rd_data(0)           <= r_tx_en;

+                WHEN "1100" => o_rd_data              <= r_mac(31 DOWNTO 0);

+                WHEN "1101" => o_rd_data(15 DOWNTO 0) <= r_mac(47 DOWNTO 32);

                 WHEN OTHERS => NULL;

             END CASE;

         END IF;

@@ -407,7 +407,7 @@

     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>

     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>

     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>

-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1 ms" xil_pn:valueState="non-default"/>

+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="2 ms" xil_pn:valueState="non-default"/>

     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>

     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>

     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>