initial firmware and testbed (6ba0467) - mips_sys · BlinkenArea

initial firmware and testbed

Stefan Schuermans commited on 2012-02-07 21:43:07
Showing 9 changed files, with 178 additions and 18 deletions.

.gitignore c0e132d..e4aca13
fw/.gitignore 0000000..81813a0
fw/Makefile 0000000..f725190
fw/boot.s 0000000..35cf47a
fw/lnk.cmd 0000000..c742987
fw/main.c 0000000..9aa81cb
mips_sys.xise 3c75c0f..b00b46b
system/system.vhd 1f15eab..353328b
test/testbed.vhd 0000000..f95b982

.gitignore

@@ -1,6 +1,7 @@
 *.bld
 *.cmd_log
 *.csv
+*.exe
 *.filter
 *.gise
 *.html
@@ -25,6 +26,7 @@
 *.twx
 *.txt
 *.unroutes
+*.wdb
 *.xml
 *.xpi
 *.xrpt

fw/.gitignore

View file @ 6ba0467

...	...	@@ -0,0 +1,4 @@
	1	+*.o
	2	+fw
	3	+fw.bin
	4	+fw.dat

fw/Makefile

View file @ 6ba0467

...	...	@@ -0,0 +1,31 @@
	1	+CC=mipsel-elf-gcc
	2	+LD=mipsel-elf-ld
	3	+OBJCOPY=mipsel-elf-objcopy
	4	+CFLAGS=-Wall -Wextra
	5	+LFLAGS=
	6	+
	7	+.phony: all clean
	8	+
	9	+all: fw.dat
	10	+
	11	+%.o: %.c
	12	+ $(CC) $(CFLAGS) -c -o $@ $<
	13	+
	14	+%.o: %.s
	15	+ $(CC) $(CFLAGS) -c -o $@ $<
	16	+
	17	+fw.o: main.o
	18	+ $(LD) $(LFLAGS) -r -o $@ $^
	19	+
	20	+fw: lnk.cmd boot.o fw.o
	21	+ $(LD) $(LFLAGS) -T lnk.cmd -o $@ boot.o fw.o
	22	+
	23	+fw.bin: fw
	24	+ $(OBJCOPY) -O binary $< $@
	25	+
	26	+fw.dat: fw.bin
	27	+ hexdump -e '1/4 "%d\n"' -v $< >$@
	28	+
	29	+clean:
	30	+ rm -f *.o fw fw.bin fw.dat
	31	+

fw/boot.s

View file @ 6ba0467

...	...	@@ -0,0 +1,2 @@
	1	+ lui $sp,0x0001
	2	+ ori $sp,0xFFFF

fw/lnk.cmd

View file @ 6ba0467

...	...	@@ -0,0 +1,9 @@
	1	+SECTIONS
	2	+{
	3	+ . = 0x00000000;
	4	+ .text : { *(.text) }
	5	+ . = 0x00000800;
	6	+ .data : { *(.data) }
	7	+ .bss : { *(.bss) }
	8	+}
	9	+

fw/main.c

View file @ 6ba0467

...	...	@@ -0,0 +1,12 @@
	1	+int global = 1;
	2	+
	3	+int main()
	4	+{
	5	+ volatile int data = (volatile int )0x00;
	6	+ int i;
	7	+ for (i = 0; i < 10; ++i)
	8	+ data[i] = i;
	9	+
	10	+ return 0;
	11	+}
	12	+

mips_sys.xise

View file @ 6ba0467

@@ -16,19 +16,19 @@
 
   <files>
     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
@@ -38,36 +38,42 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="system/ram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="system/dpram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+    </file>
+    <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
     </file>
   </files>
 
@@ -294,7 +300,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/e_testbed" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.e_testbed" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -310,7 +317,7 @@
     <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.e_testbed" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -360,7 +367,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|e_testbed|a_testbed" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="mips_sys" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

system/system.vhd

View file @ 6ba0467

@@ -6,6 +6,7 @@ ENTITY e_system IS
     PORT (
         rst:          IN  std_logic;
         clk:          IN  std_logic;
+        i_core_stall: IN  std_logic;
         i_prg_addr:   IN  std_logic_vector(31 DOWNTO 0);
         i_prg_data:   IN  std_logic_vector(31 DOWNTO 0);
         i_prg_en:     IN  std_logic;
@@ -71,7 +72,7 @@ BEGIN
         PORT MAP (
             rst            => rst,
             clk            => clk,
-            i_stall        => '0',
+            i_stall        => i_core_stall,
             o_instr_addr   => s_instr_addr,
             i_instr_data   => s_instr_data,
             o_data_addr    => s_data_addr,

test/testbed.vhd

View file @ 6ba0467

...	...	@@ -0,0 +1,92 @@
	1	+LIBRARY ieee;
	2	+USE ieee.std_logic_1164.all;
	3	+USE ieee.numeric_std.all;
	4	+USE std.textio.all;
	5	+
	6	+ENTITY e_testbed IS
	7	+END ENTITY e_testbed;
	8	+
	9	+ARCHITECTURE a_testbed OF e_testbed IS
	10	+
	11	+ COMPONENT e_system IS
	12	+ PORT (
	13	+ rst: IN std_logic;
	14	+ clk: IN std_logic;
	15	+ i_core_stall: IN std_logic;
	16	+ i_prg_addr: IN std_logic_vector(31 DOWNTO 0);
	17	+ i_prg_data: IN std_logic_vector(31 DOWNTO 0);
	18	+ i_prg_en: IN std_logic;
	19	+ o_dummy: OUT std_logic_vector(31 DOWNTO 0)
	20	+ );
	21	+ END COMPONENT e_system;
	22	+
	23	+ SIGNAL s_rst: std_logic;
	24	+ SIGNAL s_clk: std_logic;
	25	+ SIGNAL s_core_stall: std_logic;
	26	+ SIGNAL s_prg_addr: std_logic_vector(31 DOWNTO 0);
	27	+ SIGNAL s_prg_data: std_logic_vector(31 DOWNTO 0);
	28	+ SIGNAL s_prg_en: std_logic;
	29	+ SIGNAL s_dummy: std_logic_vector(31 DOWNTO 0);
	30	+
	31	+BEGIN
	32	+
	33	+ system: e_system
	34	+ PORT MAP (
	35	+ clk => s_clk,
	36	+ rst => s_rst,
	37	+ i_core_stall => s_core_stall,
	38	+ i_prg_addr => s_prg_addr,
	39	+ i_prg_data => s_prg_data,
	40	+ i_prg_en => s_prg_en,
	41	+ o_dummy => s_dummy
	42	+ );
	43	+
	44	+ p_rst_clk: PROCESS
	45	+ FILE f_data: text IS "fw/fw.dat";
	46	+ VARIABLE v_line: line;
	47	+ VARIABLE v_addr: integer;
	48	+ VARIABLE v_data: integer;
	49	+ BEGIN
	50	+ s_rst <= '0';
	51	+ s_clk <= '0';
	52	+ s_core_stall <= '1';
	53	+ s_prg_addr <= (OTHERS => '0');
	54	+ s_prg_data <= (OTHERS => '0');
	55	+ s_prg_en <= '0';
	56	+
	57	+ WAIT FOR 1 ps;
	58	+ s_rst <= '1';
	59	+ WAIT FOR 1 ps;
	60	+ s_rst <= '0';
	61	+
	62	+ s_prg_en <= '1';
	63	+ v_addr := 0;
	64	+ WHILE NOT endfile(f_data) LOOP
	65	+ readline(f_data, v_line);
	66	+ read(v_line, v_data);
	67	+ s_prg_addr <= std_logic_vector(to_unsigned(v_addr, 32));
	68	+ s_prg_data <= std_logic_vector(to_unsigned(v_data, 32));
	69	+ WAIT FOR 1 ps;
	70	+ s_clk <= '1';
	71	+ WAIT FOR 1 ps;
	72	+ s_clk <= '0';
	73	+ v_addr := v_addr + 4;
	74	+ END LOOP;
	75	+ s_prg_en <= '0';
	76	+
	77	+ WAIT FOR 10 ns;
	78	+ s_rst <= '1';
	79	+ WAIT FOR 10 ns;
	80	+ s_rst <= '0';
	81	+
	82	+ s_core_stall <= '0';
	83	+ WHILE TRUE LOOP
	84	+ WAIT FOR 10 ns;
	85	+ s_clk <= '1';
	86	+ WAIT FOR 10 ns;
	87	+ s_clk <= '0';
	88	+ END LOOP;
	89	+ END PROCESS p_rst_clk;
	90	+
	91	+END ARCHITECTURE a_testbed;
	92	+
0	93

...	...	@@ -1,6 +1,7 @@
1	1	*.bld
2	2	*.cmd_log
3	3	*.csv
	4	+*.exe
4	5	*.filter
5	6	*.gise
6	7	*.html
...	...	@@ -25,6 +26,7 @@
25	26	*.twx
26	27	*.txt
27	28	*.unroutes
	29	+*.wdb
28	30	*.xml
29	31	*.xpi
30	32	*.xrpt

...	...	@@ -16,19 +16,19 @@
16	16
17	17	<files>
18	18	<file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
	19	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
20	20	<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
21	21	</file>
22	22	<file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
23		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
	23	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
24	24	<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
25	25	</file>
26	26	<file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
	27	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
28	28	<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
	31	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
32	32	<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
33	33	</file>
34	34	<file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
...	...	@@ -38,36 +38,42 @@
38	38	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
39	39	</file>
40	40	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
41		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
	41	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
42	42	<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
43	43	</file>
44	44	<file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
45		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
	45	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
46	46	<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
47	47	</file>
48	48	<file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
49		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
	49	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
50	50	<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
51	51	</file>
52	52	<file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
53		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
	53	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
54	54	<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
55	55	</file>
56	56	<file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
57		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
	57	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
58	58	<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
59	59	</file>
60	60	<file xil_pn:name="system/ram.vhd" xil_pn:type="FILE_VHDL">
61		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
62		- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
	61	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
	62	+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
63	63	</file>
64	64	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
65		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
	65	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
66	66	<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
67	67	</file>
68	68	<file xil_pn:name="system/dpram.vhd" xil_pn:type="FILE_VHDL">
69		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/>
70		- <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
	69	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
	70	+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
	71	+ </file>
	72	+ <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
	73	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
	74	+ <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
	75	+ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
	76	+ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
71	77	</file>
72	78	</files>
73	79
...	...	@@ -294,7 +300,8 @@
294	300	<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
295	301	<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
296	302	<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
297		- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
	303	+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/e_testbed" xil_pn:valueState="non-default"/>
	304	+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.e_testbed" xil_pn:valueState="non-default"/>
298	305	<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
299	306	<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
300	307	<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
...	...	@@ -310,7 +317,7 @@
310	317	<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
311	318	<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
312	319	<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
313		- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
	320	+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.e_testbed" xil_pn:valueState="default"/>
314	321	<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
315	322	<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
316	323	<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
...	...	@@ -360,7 +367,7 @@
360	367	<!-- -->
361	368	<!-- The following properties are for internal use only. These should not be modified.-->
362	369	<!-- -->
363		- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
	370	+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture\|e_testbed\|a_testbed" xil_pn:valueState="non-default"/>
364	371	<property xil_pn:name="PROP_DesignName" xil_pn:value="mips_sys" xil_pn:valueState="non-default"/>
365	372	<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
366	373	<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

...	...	@@ -6,6 +6,7 @@ ENTITY e_system IS
6	6	PORT (
7	7	rst: IN std_logic;
8	8	clk: IN std_logic;
	9	+ i_core_stall: IN std_logic;
9	10	i_prg_addr: IN std_logic_vector(31 DOWNTO 0);
10	11	i_prg_data: IN std_logic_vector(31 DOWNTO 0);
11	12	i_prg_en: IN std_logic;
...	...	@@ -71,7 +72,7 @@ BEGIN
71	72	PORT MAP (
72	73	rst => rst,
73	74	clk => clk,
74		- i_stall => '0',
	75	+ i_stall => i_core_stall,
75	76	o_instr_addr => s_instr_addr,
76	77	i_instr_data => s_instr_data,
77	78	o_data_addr => s_data_addr,