implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) (14cef84) - mips_sys · BlinkenArea

implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet)

Parent 64053dc

Stefan Schuermans commited on 2012-03-05 22:01:56
Showing 4 changed files, with 405 additions and 73 deletions.

io/eth/eth.vhd 2825124..de1f10b
io/eth/txframe.vhd 0000000..be8e051
mips_sys.xise 00fdc73..a0c7362
system/system.vhd 22049ec..0e0227e

io/eth/eth.vhd

View file @ 14cef84

@@ -6,7 +6,7 @@ ENTITY e_io_eth IS
     PORT (
         rst:          IN  std_logic;
         clk:          IN  std_logic;
-        i_addr:       IN  std_logic_vector( 2 DOWNTO 0);
+        i_addr:       IN  std_logic_vector( 3 DOWNTO 0);
         o_rd_data:    OUT std_logic_vector(31 DOWNTO 0);
         i_rd_en:      IN  std_logic_vector( 3 DOWNTO 0);
         i_wr_data:    IN  std_logic_vector(31 DOWNTO 0);
@@ -48,6 +48,16 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
     SIGNAL s_txif_data_en:  std_logic;
     SIGNAL s_txif_data_ack: std_logic;
 
+    SIGNAL s_txframe_en:   std_logic;
+    SIGNAL s_txframe_done: std_logic;
+
+    SIGNAL s_txbuf_wr_rdy:  std_logic;
+    SIGNAL s_txbuf_wr_data: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_txbuf_wr_en:   std_logic;
+    SIGNAL s_txbuf_rd_rdy:  std_logic;
+    SIGNAL s_txbuf_rd_data: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_txbuf_rd_en:   std_logic;
+
     -- RX buffer registers
     --   start: current buffer begin
     --   cur: address of next data write
@@ -78,6 +88,23 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
     SIGNAL r_rx_new_en:    std_logic                     := '0';
     SIGNAL n_rx_new_en:    std_logic;
 
+    -- TX buffer registers
+    --   start: begin of buffer
+    --   end: address just behind buffer
+    --   en: write 1 to start transmission, returns to zero if complete
+    --   all addresses are word-aligned
+    SIGNAL r_tx_start: std_logic_vector(31 DOWNTO 0) := X"00000000";
+    SIGNAL n_tx_start: std_logic_vector(31 DOWNTO 0);
+    SIGNAL r_tx_end:   std_logic_vector(31 DOWNTO 0) := X"00000000";
+    SIGNAL n_tx_end:   std_logic_vector(31 DOWNTO 0);
+    SIGNAL r_tx_en:    std_logic                     := '0';
+    SIGNAL n_tx_en:    std_logic;
+
+    -- TX busmaster read state machine
+    SIGNAL r_tx_pos:  std_logic_vector(31 DOWNTO 0) := X"00000000";
+    SIGNAL n_tx_pos:  std_logic_vector(31 DOWNTO 0);
+
+    -- busmaster write buffer
     SIGNAL s_wrbuf_wr_rdy:  std_logic;
     SIGNAL s_wrbuf_wr_data: std_logic_vector(63 DOWNTO 0);
     SIGNAL s_wrbuf_wr_en:   std_logic;
@@ -85,6 +112,10 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
     SIGNAL s_wrbuf_rd_data: std_logic_vector(63 DOWNTO 0);
     SIGNAL s_wrbuf_rd_en:   std_logic;
 
+    -- busmaster read flag
+    SIGNAL r_bm_rd: std_logic := '0';
+    SIGNAL n_bm_rd: std_logic;
+
     COMPONENT e_io_eth_rst IS
         PORT (
             rst:        IN  std_logic;
@@ -138,6 +169,21 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
         );
     END COMPONENT e_io_eth_txif;
 
+    COMPONENT e_io_eth_txframe IS
+        PORT (
+            rst:              IN  std_logic;
+            clk:              IN  std_logic;
+            o_if_data:        OUT std_logic_vector(7 DOWNTO 0);
+            o_if_data_en:     OUT std_logic;
+            i_if_data_ack:    IN  std_logic;
+            i_frame_en:       IN  std_logic;
+            i_frame_data:     IN  std_logic_vector(31 DOWNTO 0);
+            i_frame_data_en:  IN  std_logic;
+            o_frame_data_ack: OUT std_logic;
+            o_frame_done:     OUT std_logic
+        );
+    END COMPONENT e_io_eth_txframe;
+
     COMPONENT e_block_fifo IS
         GENERIC (
             addr_width: natural;
@@ -290,7 +336,49 @@ BEGIN
         END IF;
     END PROCESS p_rx_next;
 
-    p_rx_sync: PROCESS(rst, clk)
+    txif: e_io_eth_txif
+        PORT MAP (
+            rst          => rst,
+            clk          => clk,
+            i_data       => s_txif_data,
+            i_data_en    => s_txif_data_en,
+            o_data_ack   => s_txif_data_ack,
+            pin_i_tx_clk => pin_i_tx_clk,
+            pin_o_txd    => pin_o_txd,
+            pin_o_tx_en  => pin_o_tx_en
+        );
+
+    txframe: e_io_eth_txframe
+        PORT MAP (
+            rst              => rst,
+            clk              => clk,
+            o_if_data        => s_txif_data,
+            o_if_data_en     => s_txif_data_en,
+            i_if_data_ack    => s_txif_data_ack,
+            i_frame_en       => s_txframe_en,
+            i_frame_data     => s_txbuf_rd_data,
+            i_frame_data_en  => s_txbuf_rd_rdy,
+            o_frame_data_ack => s_txbuf_rd_en,
+            o_frame_done     => s_txframe_done
+        );
+
+    txbuf: e_block_fifo
+        GENERIC MAP (
+            addr_width => 2,
+            data_width => 32
+        )
+        PORT MAP (
+            rst       => rst,
+            clk       => clk,
+            o_wr_rdy  => s_txbuf_wr_rdy,
+            i_wr_data => s_txbuf_wr_data,
+            i_wr_en   => s_txbuf_wr_en,
+            o_rd_rdy  => s_txbuf_rd_rdy,
+            o_rd_data => s_txbuf_rd_data,
+            i_rd_en   => s_txbuf_rd_en
+        );
+
+    p_reg_sync: PROCESS(rst, clk)
     BEGIN
         IF rst = '1' THEN
             r_rx_start     <= X"00000000";
@@ -300,6 +388,9 @@ BEGIN
             r_rx_new_start <= X"00000000";
             r_rx_new_end   <= X"00000000";
             r_rx_new_en    <= '0';
+            r_tx_start     <= X"00000000";
+            r_tx_end       <= X"00000000";
+            r_tx_en        <= '0';
         ELSIF rising_edge(clk) THEN
             r_rx_start     <= n_rx_start;
             r_rx_cur       <= n_rx_cur;
@@ -308,46 +399,54 @@ BEGIN
             r_rx_new_start <= n_rx_new_start;
             r_rx_new_end   <= n_rx_new_end;
             r_rx_new_en    <= n_rx_new_en;
+            r_tx_start     <= n_tx_start;
+            r_tx_end       <= n_tx_end;
+            r_tx_en        <= n_tx_en;
         END IF;
-    END PROCESS p_rx_sync;
+    END PROCESS p_reg_sync;
 
     -- register interface write
-    p_write: PROCESS(r_rx_new_start, r_rx_new_end, r_rx_new_en,
-                     s_rx_new,
+    p_write: PROCESS(r_rx_new_start, r_rx_new_end, r_rx_new_en, s_rx_new,
+                     r_tx_start, r_tx_end, r_tx_en, s_txframe_done,
                      i_addr, i_wr_data, i_wr_en)
     BEGIN
         n_rx_new_start <= r_rx_new_start;
         n_rx_new_end   <= r_rx_new_end;
         n_rx_new_en    <= r_rx_new_en;
+        n_tx_start     <= r_tx_start;
+        n_tx_end       <= r_tx_end;
+        n_tx_en        <= r_tx_en;
+        s_txframe_en   <= '0';
         IF s_rx_new = '1' THEN
-            n_rx_new_en <= '0'; -- new buffer has been overtaken, reset new_en
+            n_rx_new_en <= '0'; -- new buffer has been overtaken, reset rx_new_en
+        END IF;
+        IF s_txframe_done = '1' THEN
+            n_tx_en <= '0'; -- TX operation completed, reset tx_en
         END IF;
         IF i_wr_en = "1111" THEN
             CASE i_addr IS
-                WHEN "100" => n_rx_new_start <= i_wr_data;
-                WHEN "101" => n_rx_new_end   <= i_wr_data;
-                WHEN "110" => n_rx_new_en    <= i_wr_data(0);
+                WHEN "0100" => n_rx_new_start <= i_wr_data;
+                WHEN "0101" => n_rx_new_end   <= i_wr_data;
+                WHEN "0110" => IF i_wr_data(0) = '1' THEN
+                                   n_rx_new_en <= '1';
+                               END IF;
+                WHEN "1000" => IF r_tx_en = '0' THEN
+                                   n_tx_start <= i_wr_data;
+                               END IF;
+                WHEN "1001" => IF r_tx_en = '0' THEN
+                                   n_tx_end <= i_wr_data;
+                               END IF;
+                WHEN "1010" => IF i_wr_data(0) = '1' THEN
+                                   IF r_tx_en = '0' THEN
+                                       s_txframe_en <= '1';
+                                   END IF;
+                                   n_tx_en <= '1';
+                               END IF;
                 WHEN OTHERS => NULL;
             END CASE;
         END IF;
     END PROCESS p_write;
 
-    txif: e_io_eth_txif
-        PORT MAP (
-            rst          => rst,
-            clk          => clk,
-            i_data       => s_txif_data,
-            i_data_en    => s_txif_data_en,
-            o_data_ack   => s_txif_data_ack,
-            pin_i_tx_clk => pin_i_tx_clk,
-            pin_o_txd    => pin_o_txd,
-            pin_o_tx_en  => pin_o_tx_en
-        );
-
-    -- TODO
-    s_txif_data    <= X"00";
-    s_txif_data_en <= '0';
-
     -- register interface read
     p_read: PROCESS(rst, clk)
     BEGIN
@@ -356,13 +455,16 @@ BEGIN
         ELSIF rising_edge(clk) THEN
             o_rd_data <= (OTHERS => '0');
             CASE i_addr IS
-                WHEN "000" => o_rd_data    <= r_rx_start;
-                WHEN "001" => o_rd_data    <= r_rx_cur;
-                WHEN "010" => o_rd_data    <= r_rx_size;
-                WHEN "011" => o_rd_data    <= r_rx_end;
-                WHEN "100" => o_rd_data    <= r_rx_new_start;
-                WHEN "101" => o_rd_data    <= r_rx_new_end;
-                WHEN "110" => o_rd_data(0) <= r_rx_new_en;
+                WHEN "0000" => o_rd_data    <= r_rx_start;
+                WHEN "0001" => o_rd_data    <= r_rx_cur;
+                WHEN "0010" => o_rd_data    <= r_rx_size;
+                WHEN "0011" => o_rd_data    <= r_rx_end;
+                WHEN "0100" => o_rd_data    <= r_rx_new_start;
+                WHEN "0101" => o_rd_data    <= r_rx_new_end;
+                WHEN "0110" => o_rd_data(0) <= r_rx_new_en;
+                WHEN "1000" => o_rd_data    <= r_tx_start;
+                WHEN "1001" => o_rd_data    <= r_tx_end;
+                WHEN "1010" => o_rd_data(0) <= r_tx_en;
                 WHEN OTHERS => NULL;
             END CASE;
         END IF;
@@ -388,20 +490,67 @@ BEGIN
             i_rd_en   => s_wrbuf_rd_en
         );
 
-    pin_o_txd   <= "0000";
-    pin_o_tx_en <= '0';
+    -- TX busmaster read state machine
+    p_tx_rd_next: PROCESS(r_tx_pos, r_tx_start, s_txframe_en, s_txbuf_wr_en)
+    BEGIN
+        n_tx_pos <= r_tx_pos;
+        IF s_txframe_en = '1' THEN
+            n_tx_pos <= r_tx_start;
+        ELSIF s_txbuf_wr_en = '1' THEN
+            n_tx_pos <= std_logic_vector(unsigned(r_tx_pos) + X"00000004");
+        END IF;
+    END PROCESS p_tx_rd_next;
+
+    p_tx_rd_sync: PROCESS(clk, rst)
+    BEGIN
+        IF rst = '1' THEN
+            r_tx_pos <= X"00000000";
+        ELSIF rising_edge(clk) THEN
+            r_tx_pos <= n_tx_pos;
+        END IF;
+    END PROCESS p_tx_rd_sync;
 
-    -- bus master write
-    p_bm_wr: PROCESS(s_wrbuf_rd_rdy, s_wrbuf_rd_data, i_bm_grant)
+    -- busmaster read completed    
+    p_bm_rd: PROCESS(r_bm_rd, i_bm_rd_data)
     BEGIN
+        s_txbuf_wr_data <= X"00000000";
+        s_txbuf_wr_en   <= '0';
+        -- read was just completed
+        IF r_bm_rd = '1' THEN
+            s_txbuf_wr_data <= i_bm_rd_data;
+            s_txbuf_wr_en   <= '1';
+        END IF;
+    END PROCESS p_bm_rd;
+
+    -- bus master write (and request side of read)
+    p_bm_wr: PROCESS(r_bm_rd,
+                     r_tx_en, r_tx_pos, r_tx_end, s_txbuf_wr_rdy,
+                     s_wrbuf_rd_rdy, s_wrbuf_rd_data, i_bm_grant)
+        VARIABLE v_read:  boolean;
+        VARIABLE v_write: boolean;
+    BEGIN
+        n_bm_rd       <= '0';
         s_wrbuf_rd_en <= '0';
         o_bm_req      <= '0';
         o_bm_addr     <= (OTHERS => '0');
         o_bm_rd_en    <= (OTHERS => '0');
         o_bm_wr_data  <= (OTHERS => '0');
         o_bm_wr_en    <= (OTHERS => '0');
-        -- process write requests from write buffer
-        IF s_wrbuf_rd_rdy = '1' THEN
+        -- check for requests
+        --   read: no read just completed, TX running, not reached end,
+        --         space in buffer
+        --   write: write request in write buffer
+        v_read  := r_bm_rd = '0' AND r_tx_en = '1' AND
+                   r_tx_pos /= r_tx_end AND s_txbuf_wr_rdy = '1';
+        v_write := s_wrbuf_rd_rdy = '1';
+        -- read access
+        IF v_read THEN
+            n_bm_rd    <= i_bm_grant;
+            o_bm_req   <= '1';
+            o_bm_addr  <= r_tx_pos;
+            o_bm_rd_en <= "1111";
+        -- write access (arbitrate with read)
+        ELSIF v_write THEN
             s_wrbuf_rd_en <= i_bm_grant;
             o_bm_req      <= '1';
             o_bm_addr     <= s_wrbuf_rd_data(63 DOWNTO 32);
@@ -410,5 +559,13 @@ BEGIN
         END IF;        
     END PROCESS p_bm_wr;
 
-END ARCHITECTURE a_io_eth;
+    p_bm_sync: PROCESS(clk, rst)
+    BEGIN
+        IF rst = '1' THEN
+            r_bm_rd <= '0';
+        ELSIF rising_edge(clk) THEN
+            r_bm_rd <= n_bm_rd;
+        END IF;
+    END PROCESS p_bm_sync;
 
+END ARCHITECTURE a_io_eth;

io/eth/txframe.vhd

View file @ 14cef84

...	...	@@ -0,0 +1,171 @@
	1	+LIBRARY IEEE;
	2	+USE IEEE.STD_LOGIC_1164.ALL;
	3	+USE IEEE.NUMERIC_STD.ALL;
	4	+
	5	+ENTITY e_io_eth_txframe IS
	6	+ PORT (
	7	+ rst: IN std_logic;
	8	+ clk: IN std_logic;
	9	+ o_if_data: OUT std_logic_vector(7 DOWNTO 0);
	10	+ o_if_data_en: OUT std_logic;
	11	+ i_if_data_ack: IN std_logic;
	12	+ i_frame_en: IN std_logic;
	13	+ i_frame_data: IN std_logic_vector(31 DOWNTO 0);
	14	+ i_frame_data_en: IN std_logic;
	15	+ o_frame_data_ack: OUT std_logic;
	16	+ o_frame_done: OUT std_logic
	17	+ );
	18	+END ENTITY e_io_eth_txframe;
	19	+
	20	+ARCHITECTURE a_io_eth_txframe OF e_io_eth_txframe IS
	21	+
	22	+ TYPE t_state IS (st_idle, st_sync, st_start, st_data, st_crc, st_gap);
	23	+
	24	+ SUBTYPE t_data_cnt IS natural RANGE 0 TO 255;
	25	+
	26	+ SIGNAL r_state: t_state := st_idle;
	27	+ SIGNAL n_state: t_state;
	28	+ SIGNAL r_data_cnt: t_data_cnt := 0;
	29	+ SIGNAL n_data_cnt: t_data_cnt;
	30	+ SIGNAL r_data: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
	31	+ SIGNAL n_data: std_logic_vector(31 DOWNTO 0);
	32	+ SIGNAL r_crc_start: std_logic := '0';
	33	+ SIGNAL n_crc_start: std_logic;
	34	+
	35	+ SIGNAL s_crc_en: std_logic;
	36	+ SIGNAL s_crc_start: std_logic;
	37	+ SIGNAL s_crc_data: std_logic_vector( 7 DOWNTO 0);
	38	+ SIGNAL s_crc_crc: std_logic_vector(31 DOWNTO 0);
	39	+
	40	+ COMPONENT e_block_crc32 IS
	41	+ PORT (
	42	+ rst: IN std_logic;
	43	+ clk: IN std_logic;
	44	+ i_en: IN std_logic;
	45	+ i_start: IN std_logic;
	46	+ i_data: IN std_logic_vector( 7 DOWNTO 0);
	47	+ o_crc: OUT std_logic_vector(31 DOWNTO 0)
	48	+ );
	49	+ END COMPONENT e_block_crc32;
	50	+
	51	+BEGIN
	52	+
	53	+ crc32: e_block_crc32
	54	+ PORT MAP (
	55	+ rst => rst,
	56	+ clk => clk,
	57	+ i_en => s_crc_en,
	58	+ i_start => s_crc_start,
	59	+ i_data => s_crc_data,
	60	+ o_crc => s_crc_crc
	61	+ );
	62	+
	63	+ p_next: PROCESS(r_state, r_data_cnt, r_data, r_crc_start,
	64	+ i_if_data_ack,
	65	+ i_frame_en, i_frame_data, i_frame_data_en,
	66	+ s_crc_crc)
	67	+ BEGIN
	68	+ n_state <= r_state;
	69	+ n_data_cnt <= r_data_cnt;
	70	+ n_data <= r_data;
	71	+ n_crc_start <= '0';
	72	+ o_if_data <= X"00";
	73	+ o_if_data_en <= '0';
	74	+ o_frame_data_ack <= '0';
	75	+ s_crc_en <= '0';
	76	+ s_crc_start <= '0';
	77	+ s_crc_data <= (OTHERS => '0');
	78	+ CASE r_state IS
	79	+ WHEN st_idle =>
	80	+ IF i_frame_en = '1' THEN
	81	+ n_state <= st_sync;
	82	+ n_data_cnt <= 7;
	83	+ END IF;
	84	+ WHEN st_sync =>
	85	+ IF i_if_data_ack = '1' THEN
	86	+ IF r_data_cnt = 1 THEN
	87	+ n_state <= st_start;
	88	+ ELSE
	89	+ n_data_cnt <= r_data_cnt - 1;
	90	+ END IF;
	91	+ END IF;
	92	+ o_if_data <= X"55";
	93	+ o_if_data_en <= '1';
	94	+ WHEN st_start =>
	95	+ IF i_if_data_ack = '1' THEN
	96	+ IF i_frame_data_en = '1' THEN
	97	+ n_state <= st_data;
	98	+ n_data_cnt <= 4;
	99	+ n_data <= i_frame_data;
	100	+ n_crc_start <= '1';
	101	+ o_frame_data_ack <= '1';
	102	+ ELSE
	103	+ n_state <= st_gap;
	104	+ n_data_cnt <= 12 * 8 * 2; -- 12 octets, x2 because of clk
	105	+ END IF;
	106	+ END IF;
	107	+ o_if_data <= X"D5";
	108	+ o_if_data_en <= '1';
	109	+ WHEN st_data =>
	110	+ IF i_if_data_ack = '1' THEN
	111	+ IF r_data_cnt = 1 THEN
	112	+ IF i_frame_data_en = '1' THEN
	113	+ n_state <= st_data;
	114	+ n_data_cnt <= 4;
	115	+ n_data <= i_frame_data;
	116	+ o_frame_data_ack <= '1';
	117	+ ELSE
	118	+ n_state <= st_crc;
	119	+ n_data_cnt <= 4;
	120	+ n_data <= s_crc_crc;
	121	+ END IF;
	122	+ ELSE
	123	+ n_data_cnt <= r_data_cnt - 1;
	124	+ n_data(23 DOWNTO 0) <= r_data(31 DOWNTO 8);
	125	+ END IF;
	126	+ END IF;
	127	+ o_if_data <= r_data(7 DOWNTO 0);
	128	+ o_if_data_en <= '1';
	129	+ s_crc_en <= '1';
	130	+ s_crc_start <= r_crc_start;
	131	+ s_crc_data <= r_data(7 DOWNTO 0);
	132	+ WHEN st_crc =>
	133	+ IF i_if_data_ack = '1' THEN
	134	+ IF r_data_cnt = 1 THEN
	135	+ n_state <= st_gap;
	136	+ n_data_cnt <= 12 * 8 * 2; -- 12 octets, x2 because of clk
	137	+ ELSE
	138	+ n_data_cnt <= r_data_cnt - 1;
	139	+ n_data(23 DOWNTO 0) <= r_data(31 DOWNTO 8);
	140	+ END IF;
	141	+ END IF;
	142	+ o_if_data <= r_data(7 DOWNTO 0);
	143	+ o_if_data_en <= '1';
	144	+ WHEN st_gap =>
	145	+ IF r_data_cnt = 1 THEN
	146	+ n_state <= st_idle;
	147	+ o_frame_done <= '1';
	148	+ ELSE
	149	+ n_data_cnt <= r_data_cnt - 1;
	150	+ END IF;
	151	+ WHEN OTHERS => NULL;
	152	+ END CASE;
	153	+ END PROCESS p_next;
	154	+
	155	+ p_sync: PROCESS(rst, clk)
	156	+ BEGIN
	157	+ IF rst = '1' THEN
	158	+ r_state <= st_idle;
	159	+ r_data_cnt <= 0;
	160	+ r_data <= (OTHERS => '0');
	161	+ r_crc_start <= '0';
	162	+ ELSIF rising_edge(clk) THEN
	163	+ r_state <= n_state;
	164	+ r_data_cnt <= n_data_cnt;
	165	+ r_data <= n_data;
	166	+ r_crc_start <= n_crc_start;
	167	+ END IF;
	168	+ END PROCESS p_sync;
	169	+
	170	+END ARCHITECTURE a_io_eth_txframe;
	171	+

mips_sys.xise

View file @ 14cef84

@@ -17,43 +17,43 @@
   <files>
     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
     </file>
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
@@ -63,11 +63,11 @@
     </file>
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -77,87 +77,91 @@
     </file>
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
     </file>
     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
     </file>
     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
     </file>
     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
     </file>
     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
     <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="io/eth/txif.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="206"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+    </file>
+    <file xil_pn:name="io/eth/txframe.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="210"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
   </files>
 

system/system.vhd

View file @ 14cef84

@@ -74,7 +74,7 @@ ARCHITECTURE a_system OF e_system IS
     SIGNAL s_uart_rd_en:   std_logic_vector( 3 DOWNTO 0);
     SIGNAL s_uart_wr_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_uart_wr_en:   std_logic_vector( 3 DOWNTO 0);
-    SIGNAL s_eth_addr:    std_logic_vector( 4 DOWNTO 0);
+    SIGNAL s_eth_addr:    std_logic_vector( 5 DOWNTO 0);
     SIGNAL s_eth_rd_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_eth_rd_en:   std_logic_vector( 3 DOWNTO 0);
     SIGNAL s_eth_wr_data: std_logic_vector(31 DOWNTO 0);
@@ -212,7 +212,7 @@ ARCHITECTURE a_system OF e_system IS
         PORT (
             rst:          IN  std_logic;
             clk:          IN  std_logic;
-            i_addr:       IN  std_logic_vector( 2 DOWNTO 0);
+            i_addr:       IN  std_logic_vector( 3 DOWNTO 0);
             o_rd_data:    OUT std_logic_vector(31 DOWNTO 0);
             i_rd_en:      IN  std_logic_vector( 3 DOWNTO 0);
             i_wr_data:    IN  std_logic_vector(31 DOWNTO 0);
@@ -393,7 +393,7 @@ BEGIN
                     s_uart_wr_data <= s_dbus_wr_data;
                     s_uart_wr_en   <= s_dbus_wr_en;
                 WHEN X"04" =>
-                    s_eth_addr    <= s_dbus_addr(4 DOWNTO 0);
+                    s_eth_addr    <= s_dbus_addr(5 DOWNTO 0);
                     s_eth_rd_en   <= s_dbus_rd_en;
                     s_eth_wr_data <= s_dbus_wr_data;
                     s_eth_wr_en   <= s_dbus_wr_en;
@@ -499,7 +499,7 @@ BEGIN
         PORT MAP (
             rst          => rst,
             clk          => clk,
-            i_addr       => s_eth_addr(4 DOWNTO 2),
+            i_addr       => s_eth_addr(5 DOWNTO 2),
             o_rd_data    => s_eth_rd_data,
             i_rd_en      => s_eth_rd_en,
             i_wr_data    => s_eth_wr_data,


...	...	@@ -6,7 +6,7 @@ ENTITY e_io_eth IS
6	6	PORT (
7	7	rst: IN std_logic;
8	8	clk: IN std_logic;
9		- i_addr: IN std_logic_vector( 2 DOWNTO 0);
	9	+ i_addr: IN std_logic_vector( 3 DOWNTO 0);
10	10	o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
11	11	i_rd_en: IN std_logic_vector( 3 DOWNTO 0);
12	12	i_wr_data: IN std_logic_vector(31 DOWNTO 0);
...	...	@@ -48,6 +48,16 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
48	48	SIGNAL s_txif_data_en: std_logic;
49	49	SIGNAL s_txif_data_ack: std_logic;
50	50
	51	+ SIGNAL s_txframe_en: std_logic;
	52	+ SIGNAL s_txframe_done: std_logic;
	53	+
	54	+ SIGNAL s_txbuf_wr_rdy: std_logic;
	55	+ SIGNAL s_txbuf_wr_data: std_logic_vector(31 DOWNTO 0);
	56	+ SIGNAL s_txbuf_wr_en: std_logic;
	57	+ SIGNAL s_txbuf_rd_rdy: std_logic;
	58	+ SIGNAL s_txbuf_rd_data: std_logic_vector(31 DOWNTO 0);
	59	+ SIGNAL s_txbuf_rd_en: std_logic;
	60	+
51	61	-- RX buffer registers
52	62	-- start: current buffer begin
53	63	-- cur: address of next data write
...	...	@@ -78,6 +88,23 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
78	88	SIGNAL r_rx_new_en: std_logic := '0';
79	89	SIGNAL n_rx_new_en: std_logic;
80	90
	91	+ -- TX buffer registers
	92	+ -- start: begin of buffer
	93	+ -- end: address just behind buffer
	94	+ -- en: write 1 to start transmission, returns to zero if complete
	95	+ -- all addresses are word-aligned
	96	+ SIGNAL r_tx_start: std_logic_vector(31 DOWNTO 0) := X"00000000";
	97	+ SIGNAL n_tx_start: std_logic_vector(31 DOWNTO 0);
	98	+ SIGNAL r_tx_end: std_logic_vector(31 DOWNTO 0) := X"00000000";
	99	+ SIGNAL n_tx_end: std_logic_vector(31 DOWNTO 0);
	100	+ SIGNAL r_tx_en: std_logic := '0';
	101	+ SIGNAL n_tx_en: std_logic;
	102	+
	103	+ -- TX busmaster read state machine
	104	+ SIGNAL r_tx_pos: std_logic_vector(31 DOWNTO 0) := X"00000000";
	105	+ SIGNAL n_tx_pos: std_logic_vector(31 DOWNTO 0);
	106	+
	107	+ -- busmaster write buffer
81	108	SIGNAL s_wrbuf_wr_rdy: std_logic;
82	109	SIGNAL s_wrbuf_wr_data: std_logic_vector(63 DOWNTO 0);
83	110	SIGNAL s_wrbuf_wr_en: std_logic;
...	...	@@ -85,6 +112,10 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
85	112	SIGNAL s_wrbuf_rd_data: std_logic_vector(63 DOWNTO 0);
86	113	SIGNAL s_wrbuf_rd_en: std_logic;
87	114
	115	+ -- busmaster read flag
	116	+ SIGNAL r_bm_rd: std_logic := '0';
	117	+ SIGNAL n_bm_rd: std_logic;
	118	+
88	119	COMPONENT e_io_eth_rst IS
89	120	PORT (
90	121	rst: IN std_logic;
...	...	@@ -138,6 +169,21 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
138	169	);
139	170	END COMPONENT e_io_eth_txif;
140	171
	172	+ COMPONENT e_io_eth_txframe IS
	173	+ PORT (
	174	+ rst: IN std_logic;
	175	+ clk: IN std_logic;
	176	+ o_if_data: OUT std_logic_vector(7 DOWNTO 0);
	177	+ o_if_data_en: OUT std_logic;
	178	+ i_if_data_ack: IN std_logic;
	179	+ i_frame_en: IN std_logic;
	180	+ i_frame_data: IN std_logic_vector(31 DOWNTO 0);
	181	+ i_frame_data_en: IN std_logic;
	182	+ o_frame_data_ack: OUT std_logic;
	183	+ o_frame_done: OUT std_logic
	184	+ );
	185	+ END COMPONENT e_io_eth_txframe;
	186	+
141	187	COMPONENT e_block_fifo IS
142	188	GENERIC (
143	189	addr_width: natural;
...	...	@@ -290,7 +336,49 @@ BEGIN
290	336	END IF;
291	337	END PROCESS p_rx_next;
292	338
293		- p_rx_sync: PROCESS(rst, clk)
	339	+ txif: e_io_eth_txif
	340	+ PORT MAP (
	341	+ rst => rst,
	342	+ clk => clk,
	343	+ i_data => s_txif_data,
	344	+ i_data_en => s_txif_data_en,
	345	+ o_data_ack => s_txif_data_ack,
	346	+ pin_i_tx_clk => pin_i_tx_clk,
	347	+ pin_o_txd => pin_o_txd,
	348	+ pin_o_tx_en => pin_o_tx_en
	349	+ );
	350	+
	351	+ txframe: e_io_eth_txframe
	352	+ PORT MAP (
	353	+ rst => rst,
	354	+ clk => clk,
	355	+ o_if_data => s_txif_data,
	356	+ o_if_data_en => s_txif_data_en,
	357	+ i_if_data_ack => s_txif_data_ack,
	358	+ i_frame_en => s_txframe_en,
	359	+ i_frame_data => s_txbuf_rd_data,
	360	+ i_frame_data_en => s_txbuf_rd_rdy,
	361	+ o_frame_data_ack => s_txbuf_rd_en,
	362	+ o_frame_done => s_txframe_done
	363	+ );
	364	+
	365	+ txbuf: e_block_fifo
	366	+ GENERIC MAP (
	367	+ addr_width => 2,
	368	+ data_width => 32
	369	+ )
	370	+ PORT MAP (
	371	+ rst => rst,
	372	+ clk => clk,
	373	+ o_wr_rdy => s_txbuf_wr_rdy,
	374	+ i_wr_data => s_txbuf_wr_data,
	375	+ i_wr_en => s_txbuf_wr_en,
	376	+ o_rd_rdy => s_txbuf_rd_rdy,
	377	+ o_rd_data => s_txbuf_rd_data,
	378	+ i_rd_en => s_txbuf_rd_en
	379	+ );
	380	+
	381	+ p_reg_sync: PROCESS(rst, clk)
294	382	BEGIN
295	383	IF rst = '1' THEN
296	384	r_rx_start <= X"00000000";
...	...	@@ -300,6 +388,9 @@ BEGIN
300	388	r_rx_new_start <= X"00000000";
301	389	r_rx_new_end <= X"00000000";
302	390	r_rx_new_en <= '0';
	391	+ r_tx_start <= X"00000000";
	392	+ r_tx_end <= X"00000000";
	393	+ r_tx_en <= '0';
303	394	ELSIF rising_edge(clk) THEN
304	395	r_rx_start <= n_rx_start;
305	396	r_rx_cur <= n_rx_cur;
...	...	@@ -308,46 +399,54 @@ BEGIN
308	399	r_rx_new_start <= n_rx_new_start;
309	400	r_rx_new_end <= n_rx_new_end;
310	401	r_rx_new_en <= n_rx_new_en;
	402	+ r_tx_start <= n_tx_start;
	403	+ r_tx_end <= n_tx_end;
	404	+ r_tx_en <= n_tx_en;
311	405	END IF;
312		- END PROCESS p_rx_sync;
	406	+ END PROCESS p_reg_sync;
313	407
314	408	-- register interface write
315		- p_write: PROCESS(r_rx_new_start, r_rx_new_end, r_rx_new_en,
316		- s_rx_new,
	409	+ p_write: PROCESS(r_rx_new_start, r_rx_new_end, r_rx_new_en, s_rx_new,
	410	+ r_tx_start, r_tx_end, r_tx_en, s_txframe_done,
317	411	i_addr, i_wr_data, i_wr_en)
318	412	BEGIN
319	413	n_rx_new_start <= r_rx_new_start;
320	414	n_rx_new_end <= r_rx_new_end;
321	415	n_rx_new_en <= r_rx_new_en;
	416	+ n_tx_start <= r_tx_start;
	417	+ n_tx_end <= r_tx_end;
	418	+ n_tx_en <= r_tx_en;
	419	+ s_txframe_en <= '0';
322	420	IF s_rx_new = '1' THEN
323		- n_rx_new_en <= '0'; -- new buffer has been overtaken, reset new_en
	421	+ n_rx_new_en <= '0'; -- new buffer has been overtaken, reset rx_new_en
	422	+ END IF;
	423	+ IF s_txframe_done = '1' THEN
	424	+ n_tx_en <= '0'; -- TX operation completed, reset tx_en
324	425	END IF;
325	426	IF i_wr_en = "1111" THEN
326	427	CASE i_addr IS
327		- WHEN "100" => n_rx_new_start <= i_wr_data;
328		- WHEN "101" => n_rx_new_end <= i_wr_data;
329		- WHEN "110" => n_rx_new_en <= i_wr_data(0);
	428	+ WHEN "0100" => n_rx_new_start <= i_wr_data;
	429	+ WHEN "0101" => n_rx_new_end <= i_wr_data;
	430	+ WHEN "0110" => IF i_wr_data(0) = '1' THEN
	431	+ n_rx_new_en <= '1';
	432	+ END IF;
	433	+ WHEN "1000" => IF r_tx_en = '0' THEN
	434	+ n_tx_start <= i_wr_data;
	435	+ END IF;
	436	+ WHEN "1001" => IF r_tx_en = '0' THEN
	437	+ n_tx_end <= i_wr_data;
	438	+ END IF;
	439	+ WHEN "1010" => IF i_wr_data(0) = '1' THEN
	440	+ IF r_tx_en = '0' THEN
	441	+ s_txframe_en <= '1';
	442	+ END IF;
	443	+ n_tx_en <= '1';
	444	+ END IF;
330	445	WHEN OTHERS => NULL;
331	446	END CASE;
332	447	END IF;
333	448	END PROCESS p_write;
334	449
335		- txif: e_io_eth_txif
336		- PORT MAP (
337		- rst => rst,
338		- clk => clk,
339		- i_data => s_txif_data,
340		- i_data_en => s_txif_data_en,
341		- o_data_ack => s_txif_data_ack,
342		- pin_i_tx_clk => pin_i_tx_clk,
343		- pin_o_txd => pin_o_txd,
344		- pin_o_tx_en => pin_o_tx_en
345		- );
346		-
347		- -- TODO
348		- s_txif_data <= X"00";
349		- s_txif_data_en <= '0';
350		-
351	450	-- register interface read
352	451	p_read: PROCESS(rst, clk)
353	452	BEGIN
...	...	@@ -356,13 +455,16 @@ BEGIN
356	455	ELSIF rising_edge(clk) THEN
357	456	o_rd_data <= (OTHERS => '0');
358	457	CASE i_addr IS
359		- WHEN "000" => o_rd_data <= r_rx_start;
360		- WHEN "001" => o_rd_data <= r_rx_cur;
361		- WHEN "010" => o_rd_data <= r_rx_size;
362		- WHEN "011" => o_rd_data <= r_rx_end;
363		- WHEN "100" => o_rd_data <= r_rx_new_start;
364		- WHEN "101" => o_rd_data <= r_rx_new_end;
365		- WHEN "110" => o_rd_data(0) <= r_rx_new_en;
	458	+ WHEN "0000" => o_rd_data <= r_rx_start;
	459	+ WHEN "0001" => o_rd_data <= r_rx_cur;
	460	+ WHEN "0010" => o_rd_data <= r_rx_size;
	461	+ WHEN "0011" => o_rd_data <= r_rx_end;
	462	+ WHEN "0100" => o_rd_data <= r_rx_new_start;
	463	+ WHEN "0101" => o_rd_data <= r_rx_new_end;
	464	+ WHEN "0110" => o_rd_data(0) <= r_rx_new_en;
	465	+ WHEN "1000" => o_rd_data <= r_tx_start;
	466	+ WHEN "1001" => o_rd_data <= r_tx_end;
	467	+ WHEN "1010" => o_rd_data(0) <= r_tx_en;
366	468	WHEN OTHERS => NULL;
367	469	END CASE;
368	470	END IF;
...	...	@@ -388,20 +490,67 @@ BEGIN
388	490	i_rd_en => s_wrbuf_rd_en
389	491	);
390	492
391		- pin_o_txd <= "0000";
392		- pin_o_tx_en <= '0';
	493	+ -- TX busmaster read state machine
	494	+ p_tx_rd_next: PROCESS(r_tx_pos, r_tx_start, s_txframe_en, s_txbuf_wr_en)
	495	+ BEGIN
	496	+ n_tx_pos <= r_tx_pos;
	497	+ IF s_txframe_en = '1' THEN
	498	+ n_tx_pos <= r_tx_start;
	499	+ ELSIF s_txbuf_wr_en = '1' THEN
	500	+ n_tx_pos <= std_logic_vector(unsigned(r_tx_pos) + X"00000004");
	501	+ END IF;
	502	+ END PROCESS p_tx_rd_next;
	503	+
	504	+ p_tx_rd_sync: PROCESS(clk, rst)
	505	+ BEGIN
	506	+ IF rst = '1' THEN
	507	+ r_tx_pos <= X"00000000";
	508	+ ELSIF rising_edge(clk) THEN
	509	+ r_tx_pos <= n_tx_pos;
	510	+ END IF;
	511	+ END PROCESS p_tx_rd_sync;
393	512
394		- -- bus master write
395		- p_bm_wr: PROCESS(s_wrbuf_rd_rdy, s_wrbuf_rd_data, i_bm_grant)
	513	+ -- busmaster read completed
	514	+ p_bm_rd: PROCESS(r_bm_rd, i_bm_rd_data)
396	515	BEGIN
	516	+ s_txbuf_wr_data <= X"00000000";
	517	+ s_txbuf_wr_en <= '0';
	518	+ -- read was just completed
	519	+ IF r_bm_rd = '1' THEN
	520	+ s_txbuf_wr_data <= i_bm_rd_data;
	521	+ s_txbuf_wr_en <= '1';
	522	+ END IF;
	523	+ END PROCESS p_bm_rd;
	524	+
	525	+ -- bus master write (and request side of read)
	526	+ p_bm_wr: PROCESS(r_bm_rd,
	527	+ r_tx_en, r_tx_pos, r_tx_end, s_txbuf_wr_rdy,
	528	+ s_wrbuf_rd_rdy, s_wrbuf_rd_data, i_bm_grant)
	529	+ VARIABLE v_read: boolean;
	530	+ VARIABLE v_write: boolean;
	531	+ BEGIN
	532	+ n_bm_rd <= '0';
397	533	s_wrbuf_rd_en <= '0';
398	534	o_bm_req <= '0';
399	535	o_bm_addr <= (OTHERS => '0');
400	536	o_bm_rd_en <= (OTHERS => '0');
401	537	o_bm_wr_data <= (OTHERS => '0');
402	538	o_bm_wr_en <= (OTHERS => '0');
403		- -- process write requests from write buffer
404		- IF s_wrbuf_rd_rdy = '1' THEN
	539	+ -- check for requests
	540	+ -- read: no read just completed, TX running, not reached end,
	541	+ -- space in buffer
	542	+ -- write: write request in write buffer
	543	+ v_read := r_bm_rd = '0' AND r_tx_en = '1' AND
	544	+ r_tx_pos /= r_tx_end AND s_txbuf_wr_rdy = '1';
	545	+ v_write := s_wrbuf_rd_rdy = '1';
	546	+ -- read access
	547	+ IF v_read THEN
	548	+ n_bm_rd <= i_bm_grant;
	549	+ o_bm_req <= '1';
	550	+ o_bm_addr <= r_tx_pos;
	551	+ o_bm_rd_en <= "1111";
	552	+ -- write access (arbitrate with read)
	553	+ ELSIF v_write THEN
405	554	s_wrbuf_rd_en <= i_bm_grant;
406	555	o_bm_req <= '1';
407	556	o_bm_addr <= s_wrbuf_rd_data(63 DOWNTO 32);
...	...	@@ -410,5 +559,13 @@ BEGIN
410	559	END IF;
411	560	END PROCESS p_bm_wr;
412	561
413		-END ARCHITECTURE a_io_eth;
	562	+ p_bm_sync: PROCESS(clk, rst)
	563	+ BEGIN
	564	+ IF rst = '1' THEN
	565	+ r_bm_rd <= '0';
	566	+ ELSIF rising_edge(clk) THEN
	567	+ r_bm_rd <= n_bm_rd;
	568	+ END IF;
	569	+ END PROCESS p_bm_sync;
414	570
	571	+END ARCHITECTURE a_io_eth;

...	...	@@ -17,43 +17,43 @@
17	17	<files>
18	18	<file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19	19	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
20		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	20	+ <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
21	21	</file>
22	22	<file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
23	23	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
24		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	24	+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
25	25	</file>
26	26	<file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27	27	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
28		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	28	+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31	31	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
32		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	32	+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
33	33	</file>
34	34	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35	35	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
36		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	36	+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
37	37	</file>
38	38	<file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
39	39	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
40		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	40	+ <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
41	41	</file>
42	42	<file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
43	43	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
44		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	44	+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
45	45	</file>
46	46	<file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
47	47	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
48		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	48	+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
49	49	</file>
50	50	<file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
51	51	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
52		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	52	+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
53	53	</file>
54	54	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55	55	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
56		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	56	+ <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
57	57	</file>
58	58	<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59	59	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
...	...	@@ -63,11 +63,11 @@
63	63	</file>
64	64	<file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65	65	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
66		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	66	+ <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
67	67	</file>
68	68	<file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69	69	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
70		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	70	+ <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
71	71	</file>
72	72	<file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
73	73	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...	...	@@ -77,87 +77,91 @@
77	77	</file>
78	78	<file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
79	79	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
80		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	80	+ <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
81	81	</file>
82	82	<file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
83	83	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
84		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	84	+ <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
85	85	</file>
86	86	<file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
87	87	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
88		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	88	+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
89	89	</file>
90	90	<file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
91	91	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
92	92	</file>
93	93	<file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
94	94	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
95		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	95	+ <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
96	96	</file>
97	97	<file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
98	98	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
99		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	99	+ <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
100	100	</file>
101	101	<file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
102	102	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
103		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	103	+ <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
104	104	</file>
105	105	<file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
106	106	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
107		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	107	+ <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
108	108	</file>
109	109	<file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
110	110	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
111		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	111	+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
112	112	</file>
113	113	<file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
114	114	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
115		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	115	+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
116	116	</file>
117	117	<file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118	118	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119	119	</file>
120	120	<file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
121	121	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
122		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	122	+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
123	123	</file>
124	124	<file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
125	125	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
126	126	</file>
127	127	<file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
128	128	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
129		- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
	129	+ <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
130	130	</file>
131	131	<file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
132	132	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
133		- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
	133	+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
134	134	</file>
135	135	<file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
136	136	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
137		- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
	137	+ <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
138	138	</file>
139	139	<file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
140	140	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
141		- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
	141	+ <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
142	142	</file>
143	143	<file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
144	144	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
145		- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
	145	+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
146	146	</file>
147	147	<file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
148	148	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
149	149	</file>
150	150	<file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL">
151	151	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
152		- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
	152	+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
153	153	</file>
154	154	<file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
155	155	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
156		- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
	156	+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
157	157	</file>
158	158	<file xil_pn:name="io/eth/txif.vhd" xil_pn:type="FILE_VHDL">
159	159	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="206"/>
160		- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
	160	+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
	161	+ </file>
	162	+ <file xil_pn:name="io/eth/txframe.vhd" xil_pn:type="FILE_VHDL">
	163	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="210"/>
	164	+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
161	165	</file>
162	166	</files>
163	167

...	...	@@ -74,7 +74,7 @@ ARCHITECTURE a_system OF e_system IS
74	74	SIGNAL s_uart_rd_en: std_logic_vector( 3 DOWNTO 0);
75	75	SIGNAL s_uart_wr_data: std_logic_vector(31 DOWNTO 0);
76	76	SIGNAL s_uart_wr_en: std_logic_vector( 3 DOWNTO 0);
77		- SIGNAL s_eth_addr: std_logic_vector( 4 DOWNTO 0);
	77	+ SIGNAL s_eth_addr: std_logic_vector( 5 DOWNTO 0);
78	78	SIGNAL s_eth_rd_data: std_logic_vector(31 DOWNTO 0);
79	79	SIGNAL s_eth_rd_en: std_logic_vector( 3 DOWNTO 0);
80	80	SIGNAL s_eth_wr_data: std_logic_vector(31 DOWNTO 0);
...	...	@@ -212,7 +212,7 @@ ARCHITECTURE a_system OF e_system IS
212	212	PORT (
213	213	rst: IN std_logic;
214	214	clk: IN std_logic;
215		- i_addr: IN std_logic_vector( 2 DOWNTO 0);
	215	+ i_addr: IN std_logic_vector( 3 DOWNTO 0);
216	216	o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
217	217	i_rd_en: IN std_logic_vector( 3 DOWNTO 0);
218	218	i_wr_data: IN std_logic_vector(31 DOWNTO 0);
...	...	@@ -393,7 +393,7 @@ BEGIN
393	393	s_uart_wr_data <= s_dbus_wr_data;
394	394	s_uart_wr_en <= s_dbus_wr_en;
395	395	WHEN X"04" =>
396		- s_eth_addr <= s_dbus_addr(4 DOWNTO 0);
	396	+ s_eth_addr <= s_dbus_addr(5 DOWNTO 0);
397	397	s_eth_rd_en <= s_dbus_rd_en;
398	398	s_eth_wr_data <= s_dbus_wr_data;
399	399	s_eth_wr_en <= s_dbus_wr_en;
...	...	@@ -499,7 +499,7 @@ BEGIN
499	499	PORT MAP (
500	500	rst => rst,
501	501	clk => clk,
502		- i_addr => s_eth_addr(4 DOWNTO 2),
	502	+ i_addr => s_eth_addr(5 DOWNTO 2),
503	503	o_rd_data => s_eth_rd_data,
504	504	i_rd_en => s_eth_rd_en,
505	505	i_wr_data => s_eth_wr_data,
506	506