mips_sys

implented basic system with core, instr memory, data memory
Parent 9225422
Stefan Schuermans

Stefan Schuermans commited on 2012-02-06 21:28:00
Showing 4 changed files, with 218 additions and 11 deletions.

mips_sys.xise
View file @ b5b070d
... ... 
@@ -29,7 +29,7 @@
29 29 
     </file>
30 30 
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31 31 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
32 
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
32 
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
33 33 
     </file>
34 34 
     <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
35 35 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
... ... 
@@ -55,7 +55,19 @@
55 55 
     </file>
56 56 
     <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
57 57 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
58 
-      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
58 
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
59 
+    </file>
60 
+    <file xil_pn:name="system/ram.vhd" xil_pn:type="FILE_VHDL">
61 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
62 
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
63 
+    </file>
64 
+    <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
65 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="100"/>
66 
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
67 
+    </file>
68 
+    <file xil_pn:name="system/dpram.vhd" xil_pn:type="FILE_VHDL">
69 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="136"/>
70 
+      <association xil_pn:name="Implementation" xil_pn:seqID="136"/>
59 71 
     </file>
60 72 
   </files>
61 73
... ... 
@@ -160,9 +172,9 @@
160 172 
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
161 173 
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
162 174 
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
163 
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|e_mips_core|a_mips_core" xil_pn:valueState="non-default"/>
164 
-    <property xil_pn:name="Implementation Top File" xil_pn:value="mips/core.vhd" xil_pn:valueState="non-default"/>
165 
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/e_mips_core" xil_pn:valueState="non-default"/>
175 
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|e_system|a_system" xil_pn:valueState="non-default"/>
176 
+    <property xil_pn:name="Implementation Top File" xil_pn:value="system/system.vhd" xil_pn:valueState="non-default"/>
177 
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/e_system" xil_pn:valueState="non-default"/>
166 178 
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
167 179 
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
168 180 
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
... ... 
@@ -224,7 +236,7 @@
224 236 
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
225 237 
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
226 238 
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
227 
-    <property xil_pn:name="Output File Name" xil_pn:value="e_mips_core" xil_pn:valueState="default"/>
239 
+    <property xil_pn:name="Output File Name" xil_pn:value="e_system" xil_pn:valueState="default"/>
228 240 
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
229 241 
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
230 242 
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
... ... 
@@ -237,10 +249,10 @@
237 249 
     <property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
238 250 
     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
239 251 
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
240 
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="e_mips_core_map.vhd" xil_pn:valueState="default"/>
241 
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="e_mips_core_timesim.vhd" xil_pn:valueState="default"/>
242 
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="e_mips_core_synthesis.vhd" xil_pn:valueState="default"/>
243 
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="e_mips_core_translate.vhd" xil_pn:valueState="default"/>
252 
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="e_system_map.vhd" xil_pn:valueState="default"/>
253 
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="e_system_timesim.vhd" xil_pn:valueState="default"/>
254 
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="e_system_synthesis.vhd" xil_pn:valueState="default"/>
255 
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="e_system_translate.vhd" xil_pn:valueState="default"/>
244 256 
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
245 257 
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
246 258 
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
... ... 
@@ -260,7 +272,7 @@
260 272 
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
261 273 
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
262 274 
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
263 
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="e_mips_core" xil_pn:valueState="default"/>
275 
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="e_system" xil_pn:valueState="default"/>
264 276 
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
265 277 
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
266 278 
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
system/dpram.vhd
View file @ b5b070d
... ... 
@@ -0,0 +1,41 @@
1 
+LIBRARY IEEE;
2 
+USE IEEE.STD_LOGIC_1164.ALL;
3 
+USE IEEE.NUMERIC_STD.ALL;
4 
+
5 
+ENTITY e_dpram IS
6 
+    GENERIC (
7 
+        addr_width: natural;
8 
+        data_width: natural
9 
+    );
10 
+    PORT (
11 
+        clk:       IN  std_logic;
12 
+        i_rd_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
13 
+        o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
14 
+        i_wr_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
15 
+        i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
16 
+        i_wr_en:   IN  std_logic
17 
+    );
18 
+END ENTITY e_dpram;
19 
+
20 
+ARCHITECTURE a_dpram OF e_dpram IS
21 
+
22 
+    SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
23 
+    SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
24 
+    TYPE    t_buf  IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
25 
+
26 
+    SIGNAL s_buf: t_buf;
27 
+
28 
+BEGIN
29 
+
30 
+    p_dpram: PROCESS(clk)
31 
+    BEGIN
32 
+        IF rising_edge(clk) THEN
33 
+            IF i_wr_en = '1' THEN
34 
+                s_buf(to_integer(unsigned(i_wr_addr))) <= i_wr_data;
35 
+            END IF;
36 
+            o_rd_data <= s_buf(to_integer(unsigned(i_rd_addr)));
37 
+        END IF;
38 
+    END PROCESS p_dpram;
39 
+
40 
+END ARCHITECTURE a_dpram;
41 
+
system/ram.vhd
View file @ b5b070d
... ... 
@@ -0,0 +1,40 @@
1 
+LIBRARY IEEE;
2 
+USE IEEE.STD_LOGIC_1164.ALL;
3 
+USE IEEE.NUMERIC_STD.ALL;
4 
+
5 
+ENTITY e_ram IS
6 
+    GENERIC (
7 
+        addr_width: natural;
8 
+        data_width: natural
9 
+    );
10 
+    PORT (
11 
+        clk:       IN  std_logic;
12 
+        i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
13 
+        o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
14 
+        i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
15 
+        i_wr_en:   IN  std_logic
16 
+    );
17 
+END ENTITY e_ram;
18 
+
19 
+ARCHITECTURE a_ram OF e_ram IS
20 
+
21 
+    SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
22 
+    SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
23 
+    TYPE    t_buf  IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
24 
+
25 
+    SIGNAL s_buf: t_buf;
26 
+
27 
+BEGIN
28 
+
29 
+    p_ram: PROCESS(clk)
30 
+    BEGIN
31 
+        IF rising_edge(clk) THEN
32 
+            IF i_wr_en = '1' THEN
33 
+                s_buf(to_integer(unsigned(i_addr))) <= i_wr_data;
34 
+            END IF;
35 
+            o_rd_data <= s_buf(to_integer(unsigned(i_addr)));
36 
+        END IF;
37 
+    END PROCESS p_ram;
38 
+
39 
+END ARCHITECTURE a_ram;
40 
+
system/system.vhd
View file @ b5b070d
... ... 
@@ -0,0 +1,114 @@
1 
+LIBRARY IEEE;
2 
+USE IEEE.STD_LOGIC_1164.ALL;
3 
+USE IEEE.NUMERIC_STD.ALL;
4 
+
5 
+ENTITY e_system IS
6 
+    PORT (
7 
+        rst:        IN  std_logic;
8 
+        clk:        IN  std_logic;
9 
+        i_prg_addr: IN  std_logic_vector(31 DOWNTO 0);
10 
+        i_prg_data: IN  std_logic_vector(31 DOWNTO 0);
11 
+        i_prg_en:   IN  std_logic;
12 
+        o_dummy:    OUT std_logic_vector(31 DOWNTO 0)
13 
+    );
14 
+END ENTITY e_system;
15 
+
16 
+ARCHITECTURE a_system OF e_system IS
17 
+
18 
+    SIGNAL s_instr_addr:   std_logic_vector(31 DOWNTO 0);
19 
+    SIGNAL s_instr_data:   std_logic_vector(31 DOWNTO 0);
20 
+    SIGNAL s_data_addr:    std_logic_vector(31 DOWNTO 0);
21 
+    SIGNAL s_data_rd_data: std_logic_vector(31 DOWNTO 0);
22 
+    SIGNAL s_data_wr_data: std_logic_vector(31 DOWNTO 0);
23 
+    SIGNAL s_data_wr_en:   std_logic_vector( 3 DOWNTO 0);
24 
+
25 
+    COMPONENT e_mips_core IS
26 
+        PORT (
27 
+            rst:            IN  std_logic;
28 
+            clk:            IN  std_logic;
29 
+            i_stall:        IN  std_logic;
30 
+            o_instr_addr:   OUT std_logic_vector(31 DOWNTO 0);
31 
+            i_instr_data:   IN  std_logic_vector(31 DOWNTO 0);
32 
+            o_data_addr:    OUT std_logic_vector(31 DOWNTO 0);
33 
+            i_data_rd_data: IN  std_logic_vector(31 DOWNTO 0);
34 
+            o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
35 
+            o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0)
36 
+        );
37 
+    END COMPONENT e_mips_core;
38 
+
39 
+    COMPONENT e_ram IS
40 
+        GENERIC (
41 
+            addr_width: natural;
42 
+            data_width: natural
43 
+        );
44 
+        PORT (
45 
+            clk:       IN  std_logic;
46 
+            i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
47 
+            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
48 
+            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
49 
+            i_wr_en:   IN  std_logic
50 
+        );
51 
+    END COMPONENT e_ram;
52 
+
53 
+    COMPONENT e_dpram IS
54 
+        GENERIC (
55 
+            addr_width: natural;
56 
+            data_width: natural
57 
+        );
58 
+        PORT (
59 
+            clk:       IN  std_logic;
60 
+            i_rd_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
61 
+            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
62 
+            i_wr_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
63 
+            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
64 
+            i_wr_en:   IN  std_logic
65 
+        );
66 
+    END COMPONENT e_dpram;
67 
+
68 
+BEGIN
69 
+
70 
+    core: e_mips_core
71 
+        PORT MAP (
72 
+            rst            => rst,
73 
+            clk            => clk,
74 
+            i_stall        => '0',
75 
+            o_instr_addr   => s_instr_addr,
76 
+            i_instr_data   => s_instr_data,
77 
+            o_data_addr    => s_data_addr,
78 
+            i_data_rd_data => s_data_rd_data,
79 
+            o_data_wr_data => s_data_wr_data,
80 
+            o_data_wr_en   => s_data_wr_en
81 
+        );
82 
+
83 
+    instr: e_dpram
84 
+        GENERIC MAP (
85 
+            addr_width => 10,
86 
+            data_width => 32
87 
+        )
88 
+        PORT MAP (
89 
+            clk    => clk,
90 
+            i_rd_addr => s_instr_addr(11 DOWNTO 2),
91 
+            o_rd_data => s_instr_data,
92 
+            i_wr_addr => i_prg_addr(11 DOWNTO 2),
93 
+            i_wr_data => i_prg_data,
94 
+            i_wr_en   => i_prg_en
95 
+        );
96 
+
97 
+    data: FOR i IN 0 TO 3 GENERATE
98 
+        databank: e_ram
99 
+            GENERIC MAP (
100 
+                addr_width => 10,
101 
+                data_width => 8
102 
+            )
103 
+            PORT MAP (
104 
+                clk       => clk,
105 
+                i_addr    => s_data_addr(11 DOWNTO 2),
106 
+                o_rd_data => s_data_rd_data(i*8+7 DOWNTO i*8),
107 
+                i_wr_data => s_data_wr_data(i*8+7 DOWNTO i*8),
108 
+                i_wr_en   => s_data_wr_en(i)
109 
+            );
110 
+    END GENERATE data;
111 
+
112 
+    o_dummy <= s_data_wr_data;
113 
+
114 
+END ARCHITECTURE a_system;
0 115