mips_sys

second version of multiplier (slower, i.e. more stages -> faster clock)
Parent b88dab0
Stefan Schuermans

Stefan Schuermans commited on 2012-02-05 21:39:45
Showing 3 changed files, with 159 additions and 4 deletions.

mips/mul.vhd
View file @ 9225422
mips/mul_slow.vhd
View file @ 9225422
... ... 
@@ -0,0 +1,155 @@
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+LIBRARY ieee;
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+USE ieee.std_logic_1164.all;
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+USE ieee.numeric_std.all;
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+USE work.mips_types.all;
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+
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+ENTITY e_mips_mul IS
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+    PORT (
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+        rst:      IN  std_logic;
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+        clk:      IN  std_logic;
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+        i_a:      IN  std_logic_vector(31 DOWNTO 0);
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+        i_b:      IN  std_logic_vector(31 DOWNTO 0);
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+        i_signed: IN  std_logic;
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+        i_start:  IN  std_logic;
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+        o_busy:   OUT std_logic;
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+        o_res:    OUT std_logic_vector(63 DOWNTO 0)
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+    );
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+END ENTITY e_mips_mul;
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+
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+ARCHITECTURE a_mips_mul OF e_mips_mul IS
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+
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+    TYPE t_state IS (idle, mul1, add1, mul2, add2, mul3, add3, mul4, add4,
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+                     post);
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+    SIGNAL n_state: t_state;
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+    SIGNAL r_state: t_state;
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+
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+    SIGNAL n_a:   unsigned(31 DOWNTO 0);
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+    SIGNAL n_b:   unsigned(31 DOWNTO 0);
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+    SIGNAL n_neg: boolean;
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+    SIGNAL n_r:   unsigned(31 DOWNTO 0);
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+    SIGNAL n_res: unsigned(63 DOWNTO 0);
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+    SIGNAL r_a:   unsigned(31 DOWNTO 0);
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+    SIGNAL r_b:   unsigned(31 DOWNTO 0);
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+    SIGNAL r_neg: boolean;
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+    SIGNAL r_r:   unsigned(31 DOWNTO 0);
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+    SIGNAL r_res: unsigned(63 DOWNTO 0);
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+
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+BEGIN
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+
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+    p_mul: PROCESS(r_state, r_a, r_b, r_neg, r_r, r_res,
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+                   i_a, i_b, i_signed, i_start)
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+        VARIABLE v_a:   unsigned(15 DOWNTO 0);
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+        VARIABLE v_b:   unsigned(15 DOWNTO 0);
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+        VARIABLE v_res: unsigned(31 DOWNTO 0);
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+        VARIABLE v_add: unsigned(63 DOWNTO 0);
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+        VARIABLE v_sum: unsigned(63 DOWNTO 0);
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+    BEGIN
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+        o_busy  <= '0';
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+        n_state <= idle;
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+        n_a     <= r_a;
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+        n_b     <= r_b;
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+        n_neg   <= r_neg;
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+        n_res   <= r_res;
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+        v_a     := (OTHERS => '0');
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+        v_b     := (OTHERS => '0');
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+        v_add   := (OTHERS => '0');
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+        CASE r_state IS
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+            WHEN idle =>
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+                IF i_start = '1' THEN
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+                    o_busy  <= '1';
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+                    n_state <= mul1;
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+                    IF i_signed = '1' THEN
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+                        IF i_a(31) = '1' THEN
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+                            n_a <= unsigned(-signed(i_a));
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+                        ELSE
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+                            n_a <= unsigned(i_a);
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+                        END IF;
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+                        IF i_b(31) = '1' THEN
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+                            n_b <= unsigned(-signed(i_b));
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+                        ELSE
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+                            n_b <= unsigned(i_b);
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+                        END IF;
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+                        n_neg <= i_a(31) = '1' XOR i_b(31) = '1';
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+                    ELSE
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+                        n_a   <= unsigned(i_a);
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+                        n_b   <= unsigned(i_b);
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+                        n_neg <= false;
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+                    END IF;
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+                END IF;
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+            WHEN mul1 =>
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+                o_busy  <= '1';
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+                n_state <= add1;
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+                v_a     := r_a(15 DOWNTO  0);
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+                v_b     := r_b(15 DOWNTO  0);
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+            WHEN add1 =>
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+                o_busy  <= '1';
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+                n_state <= mul2;
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+                v_add := X"00000000" & r_r;
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+            WHEN mul2 =>
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+                o_busy  <= '1';
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+                n_state <= add2;
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+                v_a     := r_a(31 DOWNTO 16);
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+                v_b     := r_b(15 DOWNTO  0);
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+            WHEN add2 =>
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+                o_busy  <= '1';
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+                n_state <= mul3;
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+                v_add := X"0000" & r_r & X"0000";
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+            WHEN mul3 =>
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+                o_busy  <= '1';
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+                n_state <= add3;
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+                v_a     := r_a(15 DOWNTO  0);
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+                v_b     := r_b(31 DOWNTO 16);
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+            WHEN add3 =>
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+                o_busy  <= '1';
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+                n_state <= mul4;
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+                v_add := X"0000" & r_r & X"0000";
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+            WHEN mul4 =>
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+                o_busy  <= '1';
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+                n_state <= add4;
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+                v_a     := r_a(31 DOWNTO 16);
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+                v_b     := r_b(31 DOWNTO 16);
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+            WHEN add4 =>
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+                o_busy  <= '1';
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+                n_state <= post;
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+                v_add := r_r & X"00000000";
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+            WHEN OTHERS => NULL;
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+        END CASE;
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+        n_r <= v_a * v_b;
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+        v_sum := r_res + v_add;
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+        CASE r_state IS
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+            WHEN idle =>
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+                n_res <= (OTHERS => '0');
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+            WHEN add1 | add2 | add3 | add4 =>
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+                n_res <= v_sum;
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+            WHEN post =>
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+                IF r_neg THEN
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+                    n_res <= unsigned(-signed(r_res));
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+                ELSE
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+                    n_res <= r_res;
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+                END IF;
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+            WHEN OTHERS => NULL;
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+        END CASE;
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+    END PROCESS p_mul;
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+
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+    p_sync: PROCESS(rst, clk)
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+    BEGIN
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+        IF rst = '1' THEN
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+            r_state <= idle;
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+            r_a     <= (OTHERS => '0');
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+            r_b     <= (OTHERS => '0');
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+            r_neg   <= false;
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+            r_r     <= (OTHERS => '0');
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+            r_res   <= (OTHERS => '0');
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+        ELSIF rising_edge(clk) THEN
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+            r_state <= n_state;
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+            r_a     <= n_a;
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+            r_b     <= n_b;
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+            r_neg   <= n_neg;
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+            r_r     <= n_r;
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+            r_res   <= n_res;
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+        END IF;
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+    END PROCESS p_sync;
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+
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+    o_res <= std_logic_vector(n_res);
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+
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+END ARCHITECTURE a_mips_mul;
mips_sys.xise
View file @ 9225422
... ... 
@@ -49,14 +49,14 @@
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
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       <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
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     </file>
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-    <file xil_pn:name="mips/mul.vhd" xil_pn:type="FILE_VHDL">
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-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="93"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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-    </file>
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     <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="97"/>
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       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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     </file>
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+    <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
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+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="98"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
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+    </file>
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   </files>
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   <properties>
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