mips_sys

implemented ethernet TX interface (not tested yet)
Parent c906a48
Stefan Schuermans

Stefan Schuermans commited on 2012-03-04 21:38:35
Showing 3 changed files, with 194 additions and 31 deletions.

io/eth/eth.vhd
View file @ 64053dc
... ... 
@@ -42,6 +42,12 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
42 42 
     SIGNAL s_rxframe_done:    std_logic;
43 43 
     SIGNAL s_rxframe_err:     std_logic;
44 44
45 
+    SIGNAL s_rx_new: std_logic;
46 
+
47 
+    SIGNAL s_txif_data:     std_logic_vector(7 DOWNTO 0);
48 
+    SIGNAL s_txif_data_en:  std_logic;
49 
+    SIGNAL s_txif_data_ack: std_logic;
50 
+
45 51 
     -- RX buffer registers
46 52 
     --   start: current buffer begin
47 53 
     --   cur: address of next data write
... ... 
@@ -72,8 +78,6 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
72 78 
     SIGNAL r_rx_new_en:    std_logic                     := '0';
73 79 
     SIGNAL n_rx_new_en:    std_logic;
74 80
75 
-    SIGNAL s_rx_new: std_logic;
76 
-
77 81 
     SIGNAL s_wrbuf_wr_rdy:  std_logic;
78 82 
     SIGNAL s_wrbuf_wr_data: std_logic_vector(63 DOWNTO 0);
79 83 
     SIGNAL s_wrbuf_wr_en:   std_logic;
... ... 
@@ -121,6 +125,19 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
121 125 
         );
122 126 
     END COMPONENT e_io_eth_rxframe;
123 127
128 
+    COMPONENT e_io_eth_txif IS
129 
+        PORT (
130 
+            rst:          IN  std_logic;
131 
+            clk:          IN  std_logic;
132 
+            i_data:       IN  std_logic_vector(7 DOWNTO 0);
133 
+            i_data_en:    IN  std_logic;
134 
+            o_data_ack:   OUT std_logic;
135 
+            pin_i_tx_clk: IN  std_logic;
136 
+            pin_o_txd:    OUT std_logic_vector(3 DOWNTO 0);
137 
+            pin_o_tx_en:  OUT std_logic
138 
+        );
139 
+    END COMPONENT e_io_eth_txif;
140 
+
124 141 
     COMPONENT e_block_fifo IS
125 142 
         GENERIC (
126 143 
             addr_width: natural;
... ... 
@@ -315,6 +332,22 @@ BEGIN
315 332 
         END IF;
316 333 
     END PROCESS p_write;
317 334
335 
+    txif: e_io_eth_txif
336 
+        PORT MAP (
337 
+            rst          => rst,
338 
+            clk          => clk,
339 
+            i_data       => s_txif_data,
340 
+            i_data_en    => s_txif_data_en,
341 
+            o_data_ack   => s_txif_data_ack,
342 
+            pin_i_tx_clk => pin_i_tx_clk,
343 
+            pin_o_txd    => pin_o_txd,
344 
+            pin_o_tx_en  => pin_o_tx_en
345 
+        );
346 
+
347 
+    -- TODO
348 
+    s_txif_data    <= X"00";
349 
+    s_txif_data_en <= '0';
350 
+
318 351 
     -- register interface read
319 352 
     p_read: PROCESS(rst, clk)
320 353 
     BEGIN
io/eth/txif.vhd
View file @ 64053dc
... ... 
@@ -0,0 +1,126 @@
1 
+LIBRARY IEEE;
2 
+USE IEEE.STD_LOGIC_1164.ALL;
3 
+USE IEEE.NUMERIC_STD.ALL;
4 
+
5 
+ENTITY e_io_eth_txif IS
6 
+    PORT (
7 
+        rst:          IN  std_logic;
8 
+        clk:          IN  std_logic;
9 
+        i_data:       IN  std_logic_vector(7 DOWNTO 0);
10 
+        i_data_en:    IN  std_logic;
11 
+        o_data_ack:   OUT std_logic;
12 
+        pin_i_tx_clk: IN  std_logic;
13 
+        pin_o_txd:    OUT std_logic_vector(3 DOWNTO 0);
14 
+        pin_o_tx_en:  OUT std_logic
15 
+    );
16 
+END ENTITY e_io_eth_txif;
17 
+
18 
+ARCHITECTURE a_io_eth_txif OF e_io_eth_txif IS
19 
+
20 
+    TYPE t_out_state IS (out_idle, out_data_l, out_data_h);
21 
+
22 
+    TYPE t_in_state IS (in_idle, in_wait);
23 
+
24 
+    SIGNAL r_out_state: t_out_state                  := out_idle;
25 
+    SIGNAL r_out_data:  std_logic_vector(7 DOWNTO 0) := X"00";
26 
+
27 
+    SIGNAL r_if_tx_clk_trigger: std_logic := '0';
28 
+    SIGNAL r_if_tx_clk_detect:  std_logic := '0';
29 
+
30 
+    SIGNAL r_if_clk_data:    std_logic_vector(7 DOWNTO 0) := X"00";
31 
+    SIGNAL r_if_clk_trigger: std_logic                    := '0';
32 
+    SIGNAL r_if_clk_detect:  std_logic                    := '0';
33 
+
34 
+    SIGNAL r_in_state: t_in_state := in_idle;
35 
+
36 
+BEGIN
37 
+
38 
+    p_out: PROCESS(rst, pin_i_tx_clk)
39 
+    BEGIN
40 
+        IF rst = '1' THEN
41 
+            pin_o_txd   <= X"0";
42 
+            pin_o_tx_en <= '0';
43 
+        ELSIF rising_edge(pin_i_tx_clk) THEN
44 
+            CASE r_out_state IS
45 
+                WHEN out_idle =>
46 
+                    pin_o_txd   <= X"0";
47 
+                    pin_o_tx_en <= '0';
48 
+                WHEN out_data_l =>
49 
+                    pin_o_txd   <= r_out_data(3 DOWNTO 0);
50 
+                    pin_o_tx_en <= '1';
51 
+                WHEN out_data_h =>
52 
+                    pin_o_txd   <= r_out_data(7 DOWNTO 4);
53 
+                    pin_o_tx_en <= '1';
54 
+                WHEN OTHERS => NULL;
55 
+            END CASE;
56 
+        END IF;
57 
+    END PROCESS p_out;
58 
+
59 
+    p_if_tx_clk: PROCESS(rst, pin_i_tx_clk)
60 
+    BEGIN
61 
+        IF rst = '1' THEN
62 
+            r_out_state         <= out_idle;
63 
+            r_out_data          <= X"00";
64 
+            r_if_tx_clk_trigger <= '0';
65 
+            r_if_tx_clk_detect  <= '0';
66 
+        ELSIF rising_edge(pin_i_tx_clk) THEN
67 
+            CASE r_out_state IS
68 
+                WHEN out_idle =>
69 
+                    IF r_if_clk_trigger /= r_if_tx_clk_detect THEN
70 
+                        r_if_tx_clk_detect  <= NOT r_if_tx_clk_detect;
71 
+                        r_out_state         <= out_data_l;
72 
+                        r_out_data          <= r_if_clk_data;
73 
+                        r_if_tx_clk_trigger <= NOT r_if_tx_clk_trigger;
74 
+                    END IF;
75 
+                WHEN out_data_l =>
76 
+                    r_out_state <= out_data_h;
77 
+                WHEN out_data_h =>
78 
+                    IF r_if_clk_trigger /= r_if_tx_clk_detect THEN
79 
+                        r_if_tx_clk_detect  <= NOT r_if_tx_clk_detect;
80 
+                        r_out_state         <= out_data_l;
81 
+                        r_out_data          <= r_if_clk_data;
82 
+                        r_if_tx_clk_trigger <= NOT r_if_tx_clk_trigger;
83 
+                    ELSE
84 
+                        r_out_state <= out_idle;
85 
+                    END IF;
86 
+                WHEN OTHERS => NULL;
87 
+            END CASE;
88 
+        END IF;
89 
+    END PROCESS p_if_tx_clk;
90 
+
91 
+    p_if_clk: PROCESS(rst, clk)
92 
+    BEGIN
93 
+        IF rst = '1' THEN
94 
+            r_if_clk_data    <= X"00";
95 
+            r_if_clk_trigger <= '0';
96 
+            r_if_clk_detect  <= '0';
97 
+            r_in_state       <= in_idle;
98 
+            o_data_ack       <= '0';
99 
+        ELSIF rising_edge(clk) THEN
100 
+            o_data_ack       <= '0';
101 
+            CASE r_in_state IS
102 
+                WHEN in_idle =>
103 
+                    IF i_data_en = '1' THEN
104 
+                        r_if_clk_data    <= i_data;
105 
+                        r_if_clk_trigger <= NOT r_if_clk_trigger;
106 
+                        o_data_ack       <= '1';
107 
+                        r_in_state       <= in_wait;
108 
+                    END IF;
109 
+                WHEN in_wait =>
110 
+                    IF r_if_tx_clk_trigger /= r_if_clk_detect THEN
111 
+                        r_if_clk_detect <= NOT r_if_clk_detect;
112 
+                        IF i_data_en = '1' THEN
113 
+                            r_if_clk_data    <= i_data;
114 
+                            r_if_clk_trigger <= NOT r_if_clk_trigger;
115 
+                            o_data_ack       <= '1';
116 
+                        ELSE
117 
+                            r_in_state <= in_idle;
118 
+                        END IF;
119 
+                    END IF;
120 
+                WHEN OTHERS => NULL;
121 
+            END CASE;
122 
+        END IF;
123 
+    END PROCESS p_if_clk;
124 
+
125 
+END ARCHITECTURE a_io_eth_txif;
126 
+
mips_sys.xise
View file @ 64053dc
... ... 
@@ -17,43 +17,43 @@
17 17 
   <files>
18 18 
     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19 19 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
20 
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
20 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
21 21 
     </file>
22 22 
     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
23 23 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
24 
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
24 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
25 25 
     </file>
26 26 
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27 27 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
28 
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
28 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
29 29 
     </file>
30 30 
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31 31 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
32 
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
32 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
33 33 
     </file>
34 34 
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35 35 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
36 
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
36 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
37 37 
     </file>
38 38 
     <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
39 39 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
40 
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
40 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
41 41 
     </file>
42 42 
     <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
43 43 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
44 
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
44 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
45 45 
     </file>
46 46 
     <file xil_pn:name="mips/div.vhd" xil_pn:type="FILE_VHDL">
47 47 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
48 
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
48 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
49 49 
     </file>
50 50 
     <file xil_pn:name="mips/mul_slow.vhd" xil_pn:type="FILE_VHDL">
51 51 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
52 
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
52 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
53 53 
     </file>
54 54 
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55 55 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
56 
-      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
56 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
57 57 
     </file>
58 58 
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59 59 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
... ... 
@@ -63,11 +63,11 @@
63 63 
     </file>
64 64 
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65 65 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
66 
-      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
66 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
67 67 
     </file>
68 68 
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69 69 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
70 
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
70 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
71 71 
     </file>
72 72 
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
73 73 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
... ... 
@@ -77,83 +77,87 @@
77 77 
     </file>
78 78 
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
79 79 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
80 
-      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
80 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
81 81 
     </file>
82 82 
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
83 83 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
84 
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
84 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
85 85 
     </file>
86 86 
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
87 87 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
88 
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
88 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
89 89 
     </file>
90 90 
     <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
91 91 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
92 92 
     </file>
93 93 
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
94 94 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
95 
-      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
95 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
96 96 
     </file>
97 97 
     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
98 98 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
99 
-      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
99 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
100 100 
     </file>
101 101 
     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
102 102 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
103 
-      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
103 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
104 104 
     </file>
105 105 
     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
106 106 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
107 
-      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
107 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
108 108 
     </file>
109 109 
     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
110 110 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
111 
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
111 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
112 112 
     </file>
113 113 
     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
114 114 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
115 
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
115 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
116 116 
     </file>
117 117 
     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118 118 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119 119 
     </file>
120 120 
     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
121 121 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
122 
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
122 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
123 123 
     </file>
124 124 
     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
125 125 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
126 126 
     </file>
127 127 
     <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
128 128 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
129 
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
129 
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
130 130 
     </file>
131 131 
     <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
132 132 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
133 
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
133 
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
134 134 
     </file>
135 135 
     <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
136 136 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
137 
-      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
137 
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
138 138 
     </file>
139 139 
     <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
140 140 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
141 
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
141 
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
142 142 
     </file>
143 143 
     <file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
144 144 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
145 
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
145 
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
146 146 
     </file>
147 147 
     <file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
148 148 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
149 149 
     </file>
150 150 
     <file xil_pn:name="blocks/crc32.vhd" xil_pn:type="FILE_VHDL">
151 151 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
152 
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
152 
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
153 153 
     </file>
154 154 
     <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
155 155 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
156 
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
156 
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
157 
+    </file>
158 
+    <file xil_pn:name="io/eth/txif.vhd" xil_pn:type="FILE_VHDL">
159 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="206"/>
160 
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
157 161 
     </file>
158 162 
   </files>
159 163
160 164