add missing branch instruction to decoder (20735fb) - mips_sys · BlinkenArea

add missing branch instruction to decoder

Stefan Schuermans commited on 2012-01-24 21:52:35
Showing 3 changed files, with 23 additions and 19 deletions.

mips/decoder.vhd fb880fd..6140044
mips/types.vhd d90a93a..4f60c04
mips_sys.xise f62bf90..2d8db5c

mips/decoder.vhd

View file @ 20735fb

@@ -25,12 +25,15 @@ ARCHITECTURE a_mips_decoder OF e_mips_decoder IS
     TYPE t_enc_type IS (enc_reg, enc_imm, enc_jmp);
 
     SIGNAL s_opcode:   std_logic_vector(5 DOWNTO 0);
-    SIGNAL s_enc_type: t_enc_type;
+    SIGNAL s_ext_op:   std_logic_vector(4 DOWNTO 0);
     SIGNAL s_func:     std_logic_vector(5 DOWNTO 0);
+    SIGNAL s_enc_type: t_enc_type;
 
 BEGIN
 
     s_opcode <= i_instr(31 DOWNTO 26);
+    s_ext_op <= i_instr(20 DOWNTO 16);
+    s_func   <= i_instr( 5 DOWNTO 0);
 
     p_enc_type: PROCESS(s_opcode)
     BEGIN
@@ -76,14 +79,6 @@ BEGIN
         END CASE;
     END PROCESS p_imm_a;
 
-    p_func: PROCESS(i_instr, s_enc_type)
-    BEGIN
-        CASE s_enc_type IS
-            WHEN enc_reg => s_func <= i_instr(5 DOWNTO 0);
-            WHEN OTHERS  => s_func <= "000000";
-        END CASE;
-    END PROCESS p_func;
-
     p_imm_16: PROCESS(i_instr, s_enc_type)
     BEGIN
         CASE s_enc_type IS
@@ -100,7 +95,7 @@ BEGIN
         END CASE;
     END PROCESS p_imm_26;
 
-    p_op: PROCESS(s_opcode, s_func)
+    p_op: PROCESS(s_opcode, s_ext_op, s_func)
     BEGIN
         o_op   <= op_none;
         o_link <= link_none;
@@ -131,12 +126,19 @@ BEGIN
                     WHEN "101011" => o_op <= op_alu; o_alu <= alu_sltu;
                     WHEN OTHERS => NULL;
                 END CASE;
+            WHEN "000001" => o_op <= op_b; o_imm <= imm_16se;
+                             IF s_ext_op(0) = '1' THEN o_cmp <= cmp_gez;
+                                                  ELSE o_cmp <= cmp_ltz;
+                                                  END IF;
+                             IF s_ext_op(4) = '1' THEN o_link <= link_link;
+                                                  ELSE o_link <= link_none;
+                                                  END IF;
             WHEN "000010" => o_op <= op_j; o_imm <= imm_26;
             WHEN "000011" => o_op <= op_j; o_link <= link_link; o_imm <= imm_26;
-            WHEN "000100" => o_op <= op_b; o_cmp <= cmp_eq;
-            WHEN "000101" => o_op <= op_b; o_cmp <= cmp_ne;
-            WHEN "000110" => o_op <= op_b; o_cmp <= cmp_lez;
-            WHEN "000111" => o_op <= op_b; o_cmp <= cmp_gtz;
+            WHEN "000100" => o_op <= op_b; o_cmp <= cmp_eq; o_imm <= imm_16se;
+            WHEN "000101" => o_op <= op_b; o_cmp <= cmp_ne; o_imm <= imm_16se;
+            WHEN "000110" => o_op <= op_b; o_cmp <= cmp_lez; o_imm <= imm_16se;
+            WHEN "000111" => o_op <= op_b; o_cmp <= cmp_gtz; o_imm <= imm_16se;
             WHEN "001000" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
             WHEN "001001" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
             WHEN "001010" => o_op <= op_alu; o_alu <= alu_slt; o_imm <= imm_16se;

mips/types.vhd

View file @ 20735fb

@@ -22,8 +22,10 @@ PACKAGE mips_types IS
     TYPE t_cmp IS (
         cmp_none,
         cmp_eq,   -- equal
-        cmp_gtz,  -- greater zero
+        cmp_gez,  -- greater or equal zero
+        cmp_gtz,  -- greater than zero
         cmp_lez,  -- less or equal zero
+        cmp_ltz,  -- less than zero
         cmp_ne    -- not equal
     );
 

mips_sys.xise

View file @ 20735fb

@@ -17,7 +17,7 @@
   <files>
     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
@@ -25,11 +25,11 @@
     </file>
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -39,7 +39,7 @@
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>


...	...	@@ -25,12 +25,15 @@ ARCHITECTURE a_mips_decoder OF e_mips_decoder IS
25	25	TYPE t_enc_type IS (enc_reg, enc_imm, enc_jmp);
26	26
27	27	SIGNAL s_opcode: std_logic_vector(5 DOWNTO 0);
28		- SIGNAL s_enc_type: t_enc_type;
	28	+ SIGNAL s_ext_op: std_logic_vector(4 DOWNTO 0);
29	29	SIGNAL s_func: std_logic_vector(5 DOWNTO 0);
	30	+ SIGNAL s_enc_type: t_enc_type;
30	31
31	32	BEGIN
32	33
33	34	s_opcode <= i_instr(31 DOWNTO 26);
	35	+ s_ext_op <= i_instr(20 DOWNTO 16);
	36	+ s_func <= i_instr( 5 DOWNTO 0);
34	37
35	38	p_enc_type: PROCESS(s_opcode)
36	39	BEGIN
...	...	@@ -76,14 +79,6 @@ BEGIN
76	79	END CASE;
77	80	END PROCESS p_imm_a;
78	81
79		- p_func: PROCESS(i_instr, s_enc_type)
80		- BEGIN
81		- CASE s_enc_type IS
82		- WHEN enc_reg => s_func <= i_instr(5 DOWNTO 0);
83		- WHEN OTHERS => s_func <= "000000";
84		- END CASE;
85		- END PROCESS p_func;
86		-
87	82	p_imm_16: PROCESS(i_instr, s_enc_type)
88	83	BEGIN
89	84	CASE s_enc_type IS
...	...	@@ -100,7 +95,7 @@ BEGIN
100	95	END CASE;
101	96	END PROCESS p_imm_26;
102	97
103		- p_op: PROCESS(s_opcode, s_func)
	98	+ p_op: PROCESS(s_opcode, s_ext_op, s_func)
104	99	BEGIN
105	100	o_op <= op_none;
106	101	o_link <= link_none;
...	...	@@ -131,12 +126,19 @@ BEGIN
131	126	WHEN "101011" => o_op <= op_alu; o_alu <= alu_sltu;
132	127	WHEN OTHERS => NULL;
133	128	END CASE;
	129	+ WHEN "000001" => o_op <= op_b; o_imm <= imm_16se;
	130	+ IF s_ext_op(0) = '1' THEN o_cmp <= cmp_gez;
	131	+ ELSE o_cmp <= cmp_ltz;
	132	+ END IF;
	133	+ IF s_ext_op(4) = '1' THEN o_link <= link_link;
	134	+ ELSE o_link <= link_none;
	135	+ END IF;
134	136	WHEN "000010" => o_op <= op_j; o_imm <= imm_26;
135	137	WHEN "000011" => o_op <= op_j; o_link <= link_link; o_imm <= imm_26;
136		- WHEN "000100" => o_op <= op_b; o_cmp <= cmp_eq;
137		- WHEN "000101" => o_op <= op_b; o_cmp <= cmp_ne;
138		- WHEN "000110" => o_op <= op_b; o_cmp <= cmp_lez;
139		- WHEN "000111" => o_op <= op_b; o_cmp <= cmp_gtz;
	138	+ WHEN "000100" => o_op <= op_b; o_cmp <= cmp_eq; o_imm <= imm_16se;
	139	+ WHEN "000101" => o_op <= op_b; o_cmp <= cmp_ne; o_imm <= imm_16se;
	140	+ WHEN "000110" => o_op <= op_b; o_cmp <= cmp_lez; o_imm <= imm_16se;
	141	+ WHEN "000111" => o_op <= op_b; o_cmp <= cmp_gtz; o_imm <= imm_16se;
140	142	WHEN "001000" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
141	143	WHEN "001001" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
142	144	WHEN "001010" => o_op <= op_alu; o_alu <= alu_slt; o_imm <= imm_16se;

...	...	@@ -22,8 +22,10 @@ PACKAGE mips_types IS
22	22	TYPE t_cmp IS (
23	23	cmp_none,
24	24	cmp_eq, -- equal
25		- cmp_gtz, -- greater zero
	25	+ cmp_gez, -- greater or equal zero
	26	+ cmp_gtz, -- greater than zero
26	27	cmp_lez, -- less or equal zero
	28	+ cmp_ltz, -- less than zero
27	29	cmp_ne -- not equal
28	30	);
29	31

...	...	@@ -17,7 +17,7 @@
17	17	<files>
18	18	<file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19	19	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
20		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	20	+ <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
21	21	</file>
22	22	<file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
23	23	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
...	...	@@ -25,11 +25,11 @@
25	25	</file>
26	26	<file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27	27	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
28		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	28	+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31	31	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
32		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	32	+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
33	33	</file>
34	34	<file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
35	35	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...	...	@@ -39,7 +39,7 @@
39	39	</file>
40	40	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
41	41	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
42		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
	42	+ <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
43	43	</file>
44	44	<file xil_pn:name="mips/shifter.vhd" xil_pn:type="FILE_VHDL">
45	45	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
46	46