compare unit, initial PC ideas (fce5b4b) - mips_sys · BlinkenArea

compare unit, initial PC ideas

Parent 20735fb

Stefan Schuermans commited on 2012-01-25 18:56:29
Showing 5 changed files, with 136 additions and 29 deletions.

mips/cmp.vhd 0000000..05ccb62
mips/core.vhd 8d8204e..f109a58
mips/decoder.vhd 6140044..43e0896
mips/types.vhd 4f60c04..da3b002
mips_sys.xise 2d8db5c..fa7fa51

mips/cmp.vhd

...	...	@@ -0,0 +1,43 @@
	1	+LIBRARY ieee;
	2	+USE ieee.std_logic_1164.all;
	3	+USE ieee.numeric_std.all;
	4	+USE work.mips_types.all;
	5	+
	6	+ENTITY e_mips_cmp IS
	7	+ PORT (
	8	+ i_cmp: IN t_cmp;
	9	+ i_op1: IN std_logic_vector(31 DOWNTO 0);
	10	+ i_op2: IN std_logic_vector(31 DOWNTO 0);
	11	+ o_res: OUT std_logic
	12	+ );
	13	+END ENTITY e_mips_cmp;
	14	+
	15	+ARCHITECTURE a_mips_cmp OF e_mips_cmp IS
	16	+
	17	+BEGIN
	18	+
	19	+ p_cmp: PROCESS(i_cmp, i_op1, i_op2)
	20	+ VARIABLE v_op1_s: signed(31 DOWNTO 0);
	21	+ VARIABLE v_op2_s: signed(31 DOWNTO 0);
	22	+ VARIABLE v_res: boolean;
	23	+ BEGIN
	24	+ v_op1_s := signed(i_op1);
	25	+ v_op2_s := signed(i_op2);
	26	+ CASE i_cmp IS
	27	+ WHEN cmp_eq => v_res := i_op1 = i_op2;
	28	+ WHEN cmp_gez => v_res := v_op1_s >= 0;
	29	+ WHEN cmp_gtz => v_res := v_op1_s > 0;
	30	+ WHEN cmp_lez => v_res := v_op1_s <= 0;
	31	+ WHEN cmp_ltz => v_res := v_op1_s < 0;
	32	+ WHEN cmp_ne => v_res := i_op1 /= i_op2;
	33	+ WHEN OTHERS => v_res := false;
	34	+ END CASE;
	35	+ IF v_res THEN
	36	+ o_res <= '1';
	37	+ ELSE
	38	+ o_res <= '0';
	39	+ END IF;
	40	+ END PROCESS p_cmp;
	41	+
	42	+END ARCHITECTURE a_mips_cmp;
	43	+

mips/core.vhd

View file @ fce5b4b

@@ -13,6 +13,9 @@ END ENTITY e_mips_core;
 
 ARCHITECTURE a_mips_core OF e_mips_core IS
 
+    SIGNAL r_pc: std_logic_vector(31 DOWNTO 0);
+    SIGNAL n_pc: std_logic_vector(31 DOWNTO 0);
+
     SIGNAL r_instr: std_logic_vector(31 DOWNTO 0);
 
     SIGNAL s_reg_s:  std_logic_vector( 4 DOWNTO 0);
@@ -30,9 +33,13 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
     SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
 
-    SIGNAL s_op1: std_logic_vector(31 DOWNTO 0);
-    SIGNAL s_op2: std_logic_vector(31 DOWNTO 0);
-    SIGNAL s_res: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_alu_op1: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_alu_op2: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_alu_res: std_logic_vector(31 DOWNTO 0);
+
+    SIGNAL s_cmp_op1: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_cmp_op2: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_cmp_res: std_logic;
 
     SIGNAL s_reg_wr_no:   std_logic_vector( 4 DOWNTO 0);
     SIGNAL s_reg_wr_data: std_logic_vector(31 DOWNTO 0);
@@ -78,6 +85,15 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
         );
     END COMPONENT e_mips_alu;
 
+    COMPONENT e_mips_cmp IS
+        PORT (
+            i_cmp: IN  t_cmp;
+            i_op1: IN  std_logic_vector(31 DOWNTO 0);
+            i_op2: IN  std_logic_vector(31 DOWNTO 0);
+            o_res: OUT std_logic
+        );
+    END COMPONENT e_mips_cmp;
+
 BEGIN
 
     decoder: e_mips_decoder
@@ -112,9 +128,17 @@ BEGIN
     alu: e_mips_alu
         PORT MAP (
             i_alu => s_alu,
-            i_op1 => s_op1,
-            i_op2 => s_op2,
-            o_res => s_res
+            i_op1 => s_alu_op1,
+            i_op2 => s_alu_op2,
+            o_res => s_alu_res
+        );
+
+    cmp: e_mips_cmp
+        PORT MAP (
+            i_cmp => s_cmp,
+            i_op1 => s_cmp_op1,
+            i_op2 => s_cmp_op2,
+            o_res => s_cmp_res
         );
 
     p_dummy_fetch: PROCESS(rst, clk)
@@ -129,30 +153,40 @@ BEGIN
 
     p_alu_in: PROCESS(s_op, s_imm, s_val_s, s_val_t, s_imm_a, s_imm_16)
     BEGIN
-        s_op1 <= (OTHERS => '0');
-        s_op2 <= (OTHERS => '0');
+        s_alu_op1 <= (OTHERS => '0');
+        s_alu_op2 <= (OTHERS => '0');
         IF s_op = op_alu THEN
             CASE s_imm IS
                 WHEN imm_none =>
-                    s_op1 <= s_val_s;
-                    s_op2 <= s_val_t;
+                    s_alu_op1 <= s_val_s;
+                    s_alu_op2 <= s_val_t;
                 WHEN imm_a =>
-                    s_op1(4 DOWNTO 0) <= s_imm_a;
-                    s_op2 <= s_val_t;
+                    s_alu_op1(4 DOWNTO 0) <= s_imm_a;
+                    s_alu_op2 <= s_val_t;
                 WHEN imm_16se =>
-                    s_op1 <= s_val_s;
-                    s_op2(15 DOWNTO 0) <= s_imm_16;
+                    s_alu_op1 <= s_val_s;
+                    s_alu_op2(15 DOWNTO 0) <= s_imm_16;
                     IF (s_imm_16(15) = '1') THEN
-                        s_op2(31 DOWNTO 16) <= (OTHERS => '1');
+                        s_alu_op2(31 DOWNTO 16) <= (OTHERS => '1');
                     END IF;
                 WHEN imm_16ze =>
-                    s_op1 <= s_val_s;
-                    s_op2(15 DOWNTO 0) <= s_imm_16;
+                    s_alu_op1 <= s_val_s;
+                    s_alu_op2(15 DOWNTO 0) <= s_imm_16;
                 WHEN OTHERS => NULL;
             END CASE;
         END IF;
     END PROCESS p_alu_in;
 
+    p_cmp_in: PROCESS(s_op, s_val_s, s_val_t)
+    BEGIN
+        s_cmp_op1 <= (OTHERS => '0');
+        s_cmp_op2 <= (OTHERS => '0');
+        IF s_op = op_j THEN
+            s_cmp_op1 <= s_val_s;
+            s_cmp_op2 <= s_val_t;
+        END IF;
+    END PROCESS p_cmp_in;
+
     p_reg_wr: PROCESS(s_op, s_imm, s_reg_t, s_reg_d)
     BEGIN
         s_reg_wr_no   <= (OTHERS => '0');
@@ -162,18 +196,45 @@ BEGIN
             CASE s_imm IS
                 WHEN imm_none | imm_a =>
                     s_reg_wr_no   <= s_reg_d;
-                    s_reg_wr_data <= s_res;
+                    s_reg_wr_data <= s_alu_res;
                     s_reg_wr_en   <= '1';
                 WHEN imm_16se | imm_16ze =>
                     s_reg_wr_no   <= s_reg_t;
-                    s_reg_wr_data <= s_res;
+                    s_reg_wr_data <= s_alu_res;
                     s_reg_wr_en   <= '1';
                 WHEN OTHERS => NULL;
             END CASE;
         END IF;
     END PROCESS p_reg_wr;
 
-    o_res <= s_res;
+    p_next_pc: PROCESS(s_op, s_imm, s_cmp_res, s_imm_16, s_imm_26)
+        VARIABLE v_pc:  signed(31 DOWNTO 0);
+        VARIABLE v_rel: signed(17 DOWNTO 0);
+    BEGIN
+        -- FIXME
+        IF s_cmp_res = '1' AND s_imm = imm_26 THEN
+            n_pc <= r_pc(31 DOWNTO 28) & s_imm_26 & "00";
+        ELSE
+            v_pc := signed(r_pc);
+            v_rel := to_signed(4, 18);
+            IF s_cmp_res = '1' THEN
+                v_rel := signed(s_imm_16 & "00");
+            END IF;
+            v_pc := v_pc + v_rel;
+            n_pc <= std_logic_vector(v_pc);
+        END IF;
+    END PROCESS p_next_pc;
+
+    p_sync: PROCESS(rst, clk)
+    BEGIN
+        IF rst = '1' THEN
+            r_pc <= (OTHERS => '0');
+        ELSIF rising_edge(clk) THEN
+            r_pc <= n_pc;
+        END IF;
+    END PROCESS p_sync;
+
+    o_res <= s_alu_res;
 
 END ARCHITECTURE a_mips_core;
 

mips/decoder.vhd

View file @ fce5b4b

@@ -126,7 +126,7 @@ BEGIN
                     WHEN "101011" => o_op <= op_alu; o_alu <= alu_sltu;
                     WHEN OTHERS => NULL;
                 END CASE;
-            WHEN "000001" => o_op <= op_b; o_imm <= imm_16se;
+            WHEN "000001" => o_op <= op_j; o_imm <= imm_16se;
                              IF s_ext_op(0) = '1' THEN o_cmp <= cmp_gez;
                                                   ELSE o_cmp <= cmp_ltz;
                                                   END IF;
@@ -135,10 +135,10 @@ BEGIN
                                                   END IF;
             WHEN "000010" => o_op <= op_j; o_imm <= imm_26;
             WHEN "000011" => o_op <= op_j; o_link <= link_link; o_imm <= imm_26;
-            WHEN "000100" => o_op <= op_b; o_cmp <= cmp_eq; o_imm <= imm_16se;
-            WHEN "000101" => o_op <= op_b; o_cmp <= cmp_ne; o_imm <= imm_16se;
-            WHEN "000110" => o_op <= op_b; o_cmp <= cmp_lez; o_imm <= imm_16se;
-            WHEN "000111" => o_op <= op_b; o_cmp <= cmp_gtz; o_imm <= imm_16se;
+            WHEN "000100" => o_op <= op_j; o_cmp <= cmp_eq; o_imm <= imm_16se;
+            WHEN "000101" => o_op <= op_j; o_cmp <= cmp_ne; o_imm <= imm_16se;
+            WHEN "000110" => o_op <= op_j; o_cmp <= cmp_lez; o_imm <= imm_16se;
+            WHEN "000111" => o_op <= op_j; o_cmp <= cmp_gtz; o_imm <= imm_16se;
             WHEN "001000" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
             WHEN "001001" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
             WHEN "001010" => o_op <= op_alu; o_alu <= alu_slt; o_imm <= imm_16se;

mips/types.vhd

View file @ fce5b4b

@@ -8,8 +8,7 @@ PACKAGE mips_types IS
     TYPE t_op IS (
         op_none,
         op_alu, -- ALU operation
-        op_b,   -- branch (conditional)
-        op_j    -- jump
+        op_j    -- jump or branch
     );
 
     -- link (store return address in register)

mips_sys.xise

View file @ fce5b4b

@@ -25,11 +25,11 @@
     </file>
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -45,6 +45,10 @@
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
+    <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
   </files>
 
   <properties>


...	...	@@ -13,6 +13,9 @@ END ENTITY e_mips_core;
13	13
14	14	ARCHITECTURE a_mips_core OF e_mips_core IS
15	15
	16	+ SIGNAL r_pc: std_logic_vector(31 DOWNTO 0);
	17	+ SIGNAL n_pc: std_logic_vector(31 DOWNTO 0);
	18	+
16	19	SIGNAL r_instr: std_logic_vector(31 DOWNTO 0);
17	20
18	21	SIGNAL s_reg_s: std_logic_vector( 4 DOWNTO 0);
...	...	@@ -30,9 +33,13 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
30	33	SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
31	34	SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
32	35
33		- SIGNAL s_op1: std_logic_vector(31 DOWNTO 0);
34		- SIGNAL s_op2: std_logic_vector(31 DOWNTO 0);
35		- SIGNAL s_res: std_logic_vector(31 DOWNTO 0);
	36	+ SIGNAL s_alu_op1: std_logic_vector(31 DOWNTO 0);
	37	+ SIGNAL s_alu_op2: std_logic_vector(31 DOWNTO 0);
	38	+ SIGNAL s_alu_res: std_logic_vector(31 DOWNTO 0);
	39	+
	40	+ SIGNAL s_cmp_op1: std_logic_vector(31 DOWNTO 0);
	41	+ SIGNAL s_cmp_op2: std_logic_vector(31 DOWNTO 0);
	42	+ SIGNAL s_cmp_res: std_logic;
36	43
37	44	SIGNAL s_reg_wr_no: std_logic_vector( 4 DOWNTO 0);
38	45	SIGNAL s_reg_wr_data: std_logic_vector(31 DOWNTO 0);
...	...	@@ -78,6 +85,15 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
78	85	);
79	86	END COMPONENT e_mips_alu;
80	87
	88	+ COMPONENT e_mips_cmp IS
	89	+ PORT (
	90	+ i_cmp: IN t_cmp;
	91	+ i_op1: IN std_logic_vector(31 DOWNTO 0);
	92	+ i_op2: IN std_logic_vector(31 DOWNTO 0);
	93	+ o_res: OUT std_logic
	94	+ );
	95	+ END COMPONENT e_mips_cmp;
	96	+
81	97	BEGIN
82	98
83	99	decoder: e_mips_decoder
...	...	@@ -112,9 +128,17 @@ BEGIN
112	128	alu: e_mips_alu
113	129	PORT MAP (
114	130	i_alu => s_alu,
115		- i_op1 => s_op1,
116		- i_op2 => s_op2,
117		- o_res => s_res
	131	+ i_op1 => s_alu_op1,
	132	+ i_op2 => s_alu_op2,
	133	+ o_res => s_alu_res
	134	+ );
	135	+
	136	+ cmp: e_mips_cmp
	137	+ PORT MAP (
	138	+ i_cmp => s_cmp,
	139	+ i_op1 => s_cmp_op1,
	140	+ i_op2 => s_cmp_op2,
	141	+ o_res => s_cmp_res
118	142	);
119	143
120	144	p_dummy_fetch: PROCESS(rst, clk)
...	...	@@ -129,30 +153,40 @@ BEGIN
129	153
130	154	p_alu_in: PROCESS(s_op, s_imm, s_val_s, s_val_t, s_imm_a, s_imm_16)
131	155	BEGIN
132		- s_op1 <= (OTHERS => '0');
133		- s_op2 <= (OTHERS => '0');
	156	+ s_alu_op1 <= (OTHERS => '0');
	157	+ s_alu_op2 <= (OTHERS => '0');
134	158	IF s_op = op_alu THEN
135	159	CASE s_imm IS
136	160	WHEN imm_none =>
137		- s_op1 <= s_val_s;
138		- s_op2 <= s_val_t;
	161	+ s_alu_op1 <= s_val_s;
	162	+ s_alu_op2 <= s_val_t;
139	163	WHEN imm_a =>
140		- s_op1(4 DOWNTO 0) <= s_imm_a;
141		- s_op2 <= s_val_t;
	164	+ s_alu_op1(4 DOWNTO 0) <= s_imm_a;
	165	+ s_alu_op2 <= s_val_t;
142	166	WHEN imm_16se =>
143		- s_op1 <= s_val_s;
144		- s_op2(15 DOWNTO 0) <= s_imm_16;
	167	+ s_alu_op1 <= s_val_s;
	168	+ s_alu_op2(15 DOWNTO 0) <= s_imm_16;
145	169	IF (s_imm_16(15) = '1') THEN
146		- s_op2(31 DOWNTO 16) <= (OTHERS => '1');
	170	+ s_alu_op2(31 DOWNTO 16) <= (OTHERS => '1');
147	171	END IF;
148	172	WHEN imm_16ze =>
149		- s_op1 <= s_val_s;
150		- s_op2(15 DOWNTO 0) <= s_imm_16;
	173	+ s_alu_op1 <= s_val_s;
	174	+ s_alu_op2(15 DOWNTO 0) <= s_imm_16;
151	175	WHEN OTHERS => NULL;
152	176	END CASE;
153	177	END IF;
154	178	END PROCESS p_alu_in;
155	179
	180	+ p_cmp_in: PROCESS(s_op, s_val_s, s_val_t)
	181	+ BEGIN
	182	+ s_cmp_op1 <= (OTHERS => '0');
	183	+ s_cmp_op2 <= (OTHERS => '0');
	184	+ IF s_op = op_j THEN
	185	+ s_cmp_op1 <= s_val_s;
	186	+ s_cmp_op2 <= s_val_t;
	187	+ END IF;
	188	+ END PROCESS p_cmp_in;
	189	+
156	190	p_reg_wr: PROCESS(s_op, s_imm, s_reg_t, s_reg_d)
157	191	BEGIN
158	192	s_reg_wr_no <= (OTHERS => '0');
...	...	@@ -162,18 +196,45 @@ BEGIN
162	196	CASE s_imm IS
163	197	WHEN imm_none \| imm_a =>
164	198	s_reg_wr_no <= s_reg_d;
165		- s_reg_wr_data <= s_res;
	199	+ s_reg_wr_data <= s_alu_res;
166	200	s_reg_wr_en <= '1';
167	201	WHEN imm_16se \| imm_16ze =>
168	202	s_reg_wr_no <= s_reg_t;
169		- s_reg_wr_data <= s_res;
	203	+ s_reg_wr_data <= s_alu_res;
170	204	s_reg_wr_en <= '1';
171	205	WHEN OTHERS => NULL;
172	206	END CASE;
173	207	END IF;
174	208	END PROCESS p_reg_wr;
175	209
176		- o_res <= s_res;
	210	+ p_next_pc: PROCESS(s_op, s_imm, s_cmp_res, s_imm_16, s_imm_26)
	211	+ VARIABLE v_pc: signed(31 DOWNTO 0);
	212	+ VARIABLE v_rel: signed(17 DOWNTO 0);
	213	+ BEGIN
	214	+ -- FIXME
	215	+ IF s_cmp_res = '1' AND s_imm = imm_26 THEN
	216	+ n_pc <= r_pc(31 DOWNTO 28) & s_imm_26 & "00";
	217	+ ELSE
	218	+ v_pc := signed(r_pc);
	219	+ v_rel := to_signed(4, 18);
	220	+ IF s_cmp_res = '1' THEN
	221	+ v_rel := signed(s_imm_16 & "00");
	222	+ END IF;
	223	+ v_pc := v_pc + v_rel;
	224	+ n_pc <= std_logic_vector(v_pc);
	225	+ END IF;
	226	+ END PROCESS p_next_pc;
	227	+
	228	+ p_sync: PROCESS(rst, clk)
	229	+ BEGIN
	230	+ IF rst = '1' THEN
	231	+ r_pc <= (OTHERS => '0');
	232	+ ELSIF rising_edge(clk) THEN
	233	+ r_pc <= n_pc;
	234	+ END IF;
	235	+ END PROCESS p_sync;
	236	+
	237	+ o_res <= s_alu_res;
177	238
178	239	END ARCHITECTURE a_mips_core;
179	240

...	...	@@ -126,7 +126,7 @@ BEGIN
126	126	WHEN "101011" => o_op <= op_alu; o_alu <= alu_sltu;
127	127	WHEN OTHERS => NULL;
128	128	END CASE;
129		- WHEN "000001" => o_op <= op_b; o_imm <= imm_16se;
	129	+ WHEN "000001" => o_op <= op_j; o_imm <= imm_16se;
130	130	IF s_ext_op(0) = '1' THEN o_cmp <= cmp_gez;
131	131	ELSE o_cmp <= cmp_ltz;
132	132	END IF;
...	...	@@ -135,10 +135,10 @@ BEGIN
135	135	END IF;
136	136	WHEN "000010" => o_op <= op_j; o_imm <= imm_26;
137	137	WHEN "000011" => o_op <= op_j; o_link <= link_link; o_imm <= imm_26;
138		- WHEN "000100" => o_op <= op_b; o_cmp <= cmp_eq; o_imm <= imm_16se;
139		- WHEN "000101" => o_op <= op_b; o_cmp <= cmp_ne; o_imm <= imm_16se;
140		- WHEN "000110" => o_op <= op_b; o_cmp <= cmp_lez; o_imm <= imm_16se;
141		- WHEN "000111" => o_op <= op_b; o_cmp <= cmp_gtz; o_imm <= imm_16se;
	138	+ WHEN "000100" => o_op <= op_j; o_cmp <= cmp_eq; o_imm <= imm_16se;
	139	+ WHEN "000101" => o_op <= op_j; o_cmp <= cmp_ne; o_imm <= imm_16se;
	140	+ WHEN "000110" => o_op <= op_j; o_cmp <= cmp_lez; o_imm <= imm_16se;
	141	+ WHEN "000111" => o_op <= op_j; o_cmp <= cmp_gtz; o_imm <= imm_16se;
142	142	WHEN "001000" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
143	143	WHEN "001001" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
144	144	WHEN "001010" => o_op <= op_alu; o_alu <= alu_slt; o_imm <= imm_16se;

...	...	@@ -8,8 +8,7 @@ PACKAGE mips_types IS
8	8	TYPE t_op IS (
9	9	op_none,
10	10	op_alu, -- ALU operation
11		- op_b, -- branch (conditional)
12		- op_j -- jump
	11	+ op_j -- jump or branch
13	12	);
14	13
15	14	-- link (store return address in register)

...	...	@@ -25,11 +25,11 @@
25	25	</file>
26	26	<file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27	27	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
28		- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
	28	+ <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31	31	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
32		- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
	32	+ <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
33	33	</file>
34	34	<file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
35	35	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...	...	@@ -45,6 +45,10 @@
45	45	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
46	46	<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
47	47	</file>
	48	+ <file xil_pn:name="mips/cmp.vhd" xil_pn:type="FILE_VHDL">
	49	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="89"/>
	50	+ <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
	51	+ </file>
48	52	</files>
49	53
50	54	<properties>
51	55