MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
implemented ethernet RX busmaster -> packet reception working
c906a48 @ 2012-03-03 23:42:55
| blocks | implemented ethernet RX CRC check | 2012-03-03 17:09:36 |
|---|---|---|
| constraints | timing for ethernet clocks | 2012-02-21 21:39:56 |
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
| io | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
| mips | converted core to use req and grant signals to access data bus | 2012-03-01 21:23:47 |
| stuff | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
| system | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
| test | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |
| .gitignore | impact project | 2012-02-11 00:32:06 |
| Default.wcfg | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
| mips_sys.ipf | impact project | 2012-02-11 00:32:06 |
| mips_sys.xise | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |