mips_sys

added cycle counter peripheral
Parent 7283ac4
Stefan Schuermans

Stefan Schuermans commited on 2012-02-12 00:02:27
Showing 7 changed files, with 123 additions and 16 deletions.

fw/Makefile
View file @ 3bee72b
... ... 
@@ -1,4 +1,4 @@
1 
-SRCS=main.c leds.c
1 
+SRCS=cyc_cnt.c leds.c main.c
2 2
3 3 
 CC=mipsel-elf-gcc
4 4 
 LD=mipsel-elf-ld
fw/cyc_cnt.c
View file @ 3bee72b
... ... 
@@ -0,0 +1,12 @@
1 
+#include "cyc_cnt.h"
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+
3 
+/**
4 
+ * @brief read cycle counter
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+ * @return cycle counter value
6 
+ */
7 
+unsigned int cyc_cnt_read(void)
8 
+{
9 
+  volatile unsigned int *p_cyc_cnt = (volatile unsigned int *)0x80001000;
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+  return *p_cyc_cnt;
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+}
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+
fw/cyc_cnt.h
View file @ 3bee72b
... ... 
@@ -0,0 +1,11 @@
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+#ifndef CYC_CNT_H
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+#define CYC_CNT_H
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+
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+/**
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+ * @brief read cycle counter
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+ * @return cycle counter value
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+ */
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+unsigned int cyc_cnt_read(void);
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+
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+#endif /* #ifndef CYC_CNT_H */
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+
fw/main.c
View file @ 3bee72b
... ... 
@@ -1,19 +1,22 @@
1 
+#include "cyc_cnt.h"
1 2 
 #include "leds.h"
2 3
3 4 
 volatile int data[100];
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5 6 
 void delay()
6 7 
 {
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-  unsigned int i, j;
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-  for (j = 0; j < 1000; ++j)
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-    for (i = 0; i < sizeof(data) / sizeof(data[0]); ++i)
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-      data[i] = i;
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+  unsigned int start = cyc_cnt_read();
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+  while (cyc_cnt_read() - start < 10000000)
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+    /* wait */;
11 11 
 }
12 12
13 13 
 int main()
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 {
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   unsigned int i;
16 16
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+  for (i = 0; i < sizeof(data) / sizeof(data[0]); ++i)
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+    data[i] = i;
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+
17 20 
   while (1) {
18 21 
     for (i = 0x1; i < 0x80; i <<= 1) {
19 22 
       leds_set_state(i);
io/cyc_cnt.vhd
View file @ 3bee72b
... ... 
@@ -0,0 +1,43 @@
1 
+LIBRARY IEEE;
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+USE IEEE.STD_LOGIC_1164.ALL;
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+USE IEEE.NUMERIC_STD.ALL;
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+
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+ENTITY e_io_cyc_cnt IS
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+    PORT (
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+        rst:        IN  std_logic;
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+        clk:        IN  std_logic;
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+        o_rd_data:  OUT std_logic_vector(31 DOWNTO 0);
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+        i_wr_data:  IN  std_logic_vector(31 DOWNTO 0);
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+        i_wr_en:    IN  std_logic
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+    );
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+END ENTITY e_io_cyc_cnt;
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+
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+ARCHITECTURE a_io_cyc_cnt OF e_io_cyc_cnt IS
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+
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+    SIGNAL n_cnt: std_logic_vector(31 DOWNTO 0);
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+    SIGNAL r_cnt: std_logic_vector(31 DOWNTO 0);
19 
+
20 
+BEGIN
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+
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+    o_rd_data <= r_cnt;
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+
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+    p_write: PROCESS(r_cnt, i_wr_data, i_wr_en)
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+    BEGIN
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+        IF i_wr_en = '1' THEN
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+            n_cnt <= i_wr_data;
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+        ELSE
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+            n_cnt <= std_logic_vector(unsigned(r_cnt) + to_unsigned(1, 32));
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+        END IF;
31 
+    END PROCESS p_write;
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+
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+    p_sync: PROCESS(rst, clk)
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+    BEGIN
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+        IF rst = '1' THEN
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+            r_cnt <= (OTHERS => '0');
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+        ELSIF rising_edge(clk) THEN
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+            r_cnt <= n_cnt;
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+        END IF;
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+    END PROCESS p_sync;
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+
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+END ARCHITECTURE a_io_cyc_cnt;
43 
+
mips_sys.xise
View file @ 3bee72b
... ... 
@@ -56,18 +56,18 @@
56 56 
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
57 57 
     </file>
58 58 
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
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-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
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+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
61 61 
     </file>
62 62 
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
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-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
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+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
64 64 
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
65 65 
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
66 66 
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
67 67 
     </file>
68 68 
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
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-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
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-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
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+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
71 71 
     </file>
72 72 
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
73 73 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
... ... 
@@ -82,11 +82,15 @@
82 82 
     <file xil_pn:name="constraints/rst.ucf" xil_pn:type="FILE_UCF">
83 83 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
84 84 
     </file>
85 
+    <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
86 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
87 
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
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+    </file>
85 89 
   </files>
86 90
87 91 
   <properties>
88 92 
     <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
89 
-    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="true" xil_pn:valueState="non-default"/>
90 94 
     <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
91 95 
     <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
92 96 
     <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
... ... 
@@ -200,7 +204,7 @@
200 204 
     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
201 205 
     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
202 206 
     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
203 
-    <property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
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+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
204 208 
     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
205 209 
     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
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     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
... ... 
@@ -230,7 +234,7 @@
230 234 
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
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     <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
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     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Speed" xil_pn:valueState="non-default"/>
234 238 
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
235 239 
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
236 240 
     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
... ... 
@@ -257,7 +261,7 @@
257 261 
     <property xil_pn:name="Package" xil_pn:value="fg484" xil_pn:valueState="non-default"/>
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     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
259 263 
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
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-    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
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+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="true" xil_pn:valueState="non-default"/>
261 265 
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
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     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
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     <property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
system/system.vhd
View file @ 3bee72b
... ... 
@@ -25,6 +25,9 @@ ARCHITECTURE a_system OF e_system IS
25 25 
     SIGNAL s_leds_rd_data: std_logic_vector( 7 DOWNTO 0);
26 26 
     SIGNAL s_leds_wr_data: std_logic_vector( 7 DOWNTO 0);
27 27 
     SIGNAL s_leds_wr_en:   std_logic;
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+    SIGNAL s_cyc_cnt_rd_data: std_logic_vector(31 DOWNTO 0);
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+    SIGNAL s_cyc_cnt_wr_data: std_logic_vector(31 DOWNTO 0);
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+    SIGNAL s_cyc_cnt_wr_en:   std_logic;
28 31
29 32 
     COMPONENT e_mips_core IS
30 33 
         PORT (
... ... 
@@ -76,6 +79,16 @@ ARCHITECTURE a_system OF e_system IS
76 79 
         );
77 80 
     END COMPONENT e_io_leds;
78 81
82 
+    COMPONENT e_io_cyc_cnt IS
83 
+        PORT (
84 
+            rst:        IN  std_logic;
85 
+            clk:        IN  std_logic;
86 
+            o_rd_data:  OUT std_logic_vector(31 DOWNTO 0);
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+            i_wr_data:  IN  std_logic_vector(31 DOWNTO 0);
88 
+            i_wr_en:    IN  std_logic
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+        );
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+    END COMPONENT e_io_cyc_cnt;
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+
79 92 
 BEGIN
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81 94 
     core: e_mips_core
... ... 
@@ -103,8 +116,12 @@ BEGIN
103 116
104 117 
     p_dbus: PROCESS(s_dbus_addr, s_dbus_wr_data, s_dbus_wr_en,
105 118 
                     s_data_rd_data,
106 
-                    s_leds_rd_data)
119 
+                    s_leds_rd_data,
120 
+                    s_cyc_cnt_rd_data)
121 
+        VARIABLE v_wr_en_word: std_logic;
107 122 
     BEGIN
123 
+        v_wr_en_word := s_dbus_wr_en(0) AND s_dbus_wr_en(1) AND
124 
+                        s_dbus_wr_en(2) AND s_dbus_wr_en(3);
108 125 
         s_dbus_rd_data <= (OTHERS => '0');
109 126 
         s_data_addr    <= (OTHERS => '0');
110 127 
         s_data_wr_data <= (OTHERS => '0');
... ... 
@@ -116,10 +133,18 @@ BEGIN
116 133 
             s_data_addr    <= s_dbus_addr;
117 134 
             s_data_wr_data <= s_dbus_wr_data;
118 135 
             s_data_wr_en   <= s_dbus_wr_en;
119 
-        ELSIF s_dbus_addr(31 DOWNTO 0) = X"80000000" THEN
136 
+        ELSIF s_dbus_addr(31 DOWNTO 16) = X"8000" THEN
137 
+            CASE s_dbus_addr(15 DOWNTO 8) IS
138 
+                WHEN X"00" =>
120 139 
                     s_dbus_rd_data <= X"000000" & s_leds_rd_data;
121 140 
                     s_leds_wr_data <= s_dbus_wr_data(7 DOWNTO 0);
122 141 
                     s_leds_wr_en   <= s_dbus_wr_en(0);
142 
+                WHEN X"10" =>
143 
+                    s_dbus_rd_data    <= s_cyc_cnt_rd_data;
144 
+                    s_cyc_cnt_wr_data <= s_dbus_wr_data;
145 
+                    s_cyc_cnt_wr_en   <= v_wr_en_word;
146 
+                WHEN OTHERS => NULL;
147 
+            END CASE;
123 148 
         END IF;
124 149 
     END PROCESS p_dbus;
125 150
... ... 
@@ -148,4 +173,13 @@ BEGIN
148 173 
             pin_o_leds => pin_o_leds
149 174 
         );
150 175
176 
+    cyc_cnt: e_io_cyc_cnt
177 
+        PORT MAP (
178 
+            rst        => rst,
179 
+            clk        => clk,
180 
+            o_rd_data  => s_cyc_cnt_rd_data,
181 
+            i_wr_data  => s_cyc_cnt_wr_data,
182 
+            i_wr_en    => s_cyc_cnt_wr_en
183 
+        );
184 
+
151 185 
 END ARCHITECTURE a_system;
152 186