mips_sys

implemented ethernet RX packet and TX clock in testbed
Parent 230fe3b
Stefan Schuermans

Stefan Schuermans commited on 2012-03-06 20:48:33
Showing 3 changed files, with 111 additions and 102 deletions.

Default.wcfg
View file @ 6f152d9
... ... 
@@ -15,7 +15,7 @@
15 15 
          </top_modules>
16 16 
       </db_ref>
17 17 
    </db_ref_list>
18 
-   <WVObjectSize size="28" />
18 
+   <WVObjectSize size="18" />
19 19 
    <wvobject fp_name="/e_testbed/s_clk" type="logic" db_ref_id="1">
20 20 
       <obj_property name="ElementShortName">s_clk</obj_property>
21 21 
       <obj_property name="ObjectShortName">s_clk</obj_property>
... ... 
@@ -37,89 +37,41 @@
37 37 
       <obj_property name="ElementShortName">pin_o_uart_tx</obj_property>
38 38 
       <obj_property name="ObjectShortName">pin_o_uart_tx</obj_property>
39 39 
    </wvobject>
40 
-   <wvobject fp_name="/e_testbed/system/core/o_instr_addr" type="array" db_ref_id="1">
41 
-      <obj_property name="ElementShortName">o_instr_addr[31:0]</obj_property>
42 
-      <obj_property name="ObjectShortName">o_instr_addr[31:0]</obj_property>
43 
-      <obj_property name="Radix">HEXRADIX</obj_property>
40 
+   <wvobject fp_name="/e_testbed/system/pin_i_eth_rx_clk" type="logic" db_ref_id="1">
41 
+      <obj_property name="ElementShortName">pin_i_eth_rx_clk</obj_property>
42 
+      <obj_property name="ObjectShortName">pin_i_eth_rx_clk</obj_property>
44 43 
    </wvobject>
45 
-   <wvobject fp_name="/e_testbed/system/core/i_instr_data" type="array" db_ref_id="1">
46 
-      <obj_property name="ElementShortName">i_instr_data[31:0]</obj_property>
47 
-      <obj_property name="ObjectShortName">i_instr_data[31:0]</obj_property>
48 
-      <obj_property name="Radix">HEXRADIX</obj_property>
49 
-   </wvobject>
50 
-   <wvobject fp_name="/e_testbed/system/core/s_stall" type="logic" db_ref_id="1">
51 
-      <obj_property name="ElementShortName">s_stall</obj_property>
52 
-      <obj_property name="ObjectShortName">s_stall</obj_property>
53 
-   </wvobject>
54 
-   <wvobject fp_name="/e_testbed/system/eth/r_rx_start" type="array" db_ref_id="1">
55 
-      <obj_property name="ElementShortName">r_rx_start[31:0]</obj_property>
56 
-      <obj_property name="ObjectShortName">r_rx_start[31:0]</obj_property>
57 
-      <obj_property name="Radix">HEXRADIX</obj_property>
58 
-   </wvobject>
59 
-   <wvobject fp_name="/e_testbed/system/eth/r_rx_cur" type="array" db_ref_id="1">
60 
-      <obj_property name="ElementShortName">r_rx_cur[31:0]</obj_property>
61 
-      <obj_property name="ObjectShortName">r_rx_cur[31:0]</obj_property>
62 
-      <obj_property name="Radix">HEXRADIX</obj_property>
63 
-   </wvobject>
64 
-   <wvobject fp_name="/e_testbed/system/eth/r_rx_size" type="array" db_ref_id="1">
65 
-      <obj_property name="ElementShortName">r_rx_size[31:0]</obj_property>
66 
-      <obj_property name="ObjectShortName">r_rx_size[31:0]</obj_property>
67 
-      <obj_property name="Radix">HEXRADIX</obj_property>
44 
+   <wvobject fp_name="/e_testbed/system/pin_i_eth_rxd" type="array" db_ref_id="1">
45 
+      <obj_property name="ElementShortName">pin_i_eth_rxd[4:0]</obj_property>
46 
+      <obj_property name="ObjectShortName">pin_i_eth_rxd[4:0]</obj_property>
68 47 
    </wvobject>
69 
-   <wvobject fp_name="/e_testbed/system/eth/r_rx_end" type="array" db_ref_id="1">
70 
-      <obj_property name="ElementShortName">r_rx_end[31:0]</obj_property>
71 
-      <obj_property name="ObjectShortName">r_rx_end[31:0]</obj_property>
72 
-      <obj_property name="Radix">HEXRADIX</obj_property>
48 
+   <wvobject fp_name="/e_testbed/system/pin_i_eth_rx_dv" type="logic" db_ref_id="1">
49 
+      <obj_property name="ElementShortName">pin_i_eth_rx_dv</obj_property>
50 
+      <obj_property name="ObjectShortName">pin_i_eth_rx_dv</obj_property>
73 51 
    </wvobject>
74 
-   <wvobject fp_name="/e_testbed/system/eth/r_rx_new_start" type="array" db_ref_id="1">
75 
-      <obj_property name="ElementShortName">r_rx_new_start[31:0]</obj_property>
76 
-      <obj_property name="ObjectShortName">r_rx_new_start[31:0]</obj_property>
77 
-      <obj_property name="Radix">HEXRADIX</obj_property>
52 
+   <wvobject fp_name="/e_testbed/system/pin_i_eth_tx_clk" type="logic" db_ref_id="1">
53 
+      <obj_property name="ElementShortName">pin_i_eth_tx_clk</obj_property>
54 
+      <obj_property name="ObjectShortName">pin_i_eth_tx_clk</obj_property>
78 55 
    </wvobject>
79 
-   <wvobject fp_name="/e_testbed/system/eth/r_rx_new_end" type="array" db_ref_id="1">
80 
-      <obj_property name="ElementShortName">r_rx_new_end[31:0]</obj_property>
81 
-      <obj_property name="ObjectShortName">r_rx_new_end[31:0]</obj_property>
56 
+   <wvobject fp_name="/e_testbed/system/pin_o_eth_txd" type="array" db_ref_id="1">
57 
+      <obj_property name="ElementShortName">pin_o_eth_txd[3:0]</obj_property>
58 
+      <obj_property name="ObjectShortName">pin_o_eth_txd[3:0]</obj_property>
82 59 
       <obj_property name="Radix">HEXRADIX</obj_property>
83 60 
    </wvobject>
84 
-   <wvobject fp_name="/e_testbed/system/eth/r_rx_new_en" type="logic" db_ref_id="1">
85 
-      <obj_property name="ElementShortName">r_rx_new_en</obj_property>
86 
-      <obj_property name="ObjectShortName">r_rx_new_en</obj_property>
87 
-   </wvobject>
88 
-   <wvobject fp_name="/e_testbed/system/eth/s_rx_new" type="logic" db_ref_id="1">
89 
-      <obj_property name="ElementShortName">s_rx_new</obj_property>
90 
-      <obj_property name="ObjectShortName">s_rx_new</obj_property>
91 
-   </wvobject>
92 
-   <wvobject fp_name="/e_testbed/system/core/o_data_req" type="logic" db_ref_id="1">
93 
-      <obj_property name="ElementShortName">o_data_req</obj_property>
94 
-      <obj_property name="ObjectShortName">o_data_req</obj_property>
61 
+   <wvobject fp_name="/e_testbed/system/pin_o_eth_tx_en" type="logic" db_ref_id="1">
62 
+      <obj_property name="ElementShortName">pin_o_eth_tx_en</obj_property>
63 
+      <obj_property name="ObjectShortName">pin_o_eth_tx_en</obj_property>
95 64 
    </wvobject>
96 
-   <wvobject fp_name="/e_testbed/system/core/i_data_grant" type="logic" db_ref_id="1">
97 
-      <obj_property name="ElementShortName">i_data_grant</obj_property>
98 
-      <obj_property name="ObjectShortName">i_data_grant</obj_property>
99 
-   </wvobject>
100 
-   <wvobject fp_name="/e_testbed/system/core/o_data_addr" type="array" db_ref_id="1">
101 
-      <obj_property name="ElementShortName">o_data_addr[31:0]</obj_property>
102 
-      <obj_property name="ObjectShortName">o_data_addr[31:0]</obj_property>
103 
-      <obj_property name="Radix">HEXRADIX</obj_property>
104 
-   </wvobject>
105 
-   <wvobject fp_name="/e_testbed/system/core/o_data_wr_data" type="array" db_ref_id="1">
106 
-      <obj_property name="ElementShortName">o_data_wr_data[31:0]</obj_property>
107 
-      <obj_property name="ObjectShortName">o_data_wr_data[31:0]</obj_property>
65 
+   <wvobject fp_name="/e_testbed/system/core/o_instr_addr" type="array" db_ref_id="1">
66 
+      <obj_property name="ElementShortName">o_instr_addr[31:0]</obj_property>
67 
+      <obj_property name="ObjectShortName">o_instr_addr[31:0]</obj_property>
108 68 
       <obj_property name="Radix">HEXRADIX</obj_property>
109 69 
    </wvobject>
110 
-   <wvobject fp_name="/e_testbed/system/core/o_data_wr_en" type="array" db_ref_id="1">
111 
-      <obj_property name="ElementShortName">o_data_wr_en[3:0]</obj_property>
112 
-      <obj_property name="ObjectShortName">o_data_wr_en[3:0]</obj_property>
113 
-   </wvobject>
114 
-   <wvobject fp_name="/e_testbed/system/core/i_data_rd_data" type="array" db_ref_id="1">
115 
-      <obj_property name="ElementShortName">i_data_rd_data[31:0]</obj_property>
116 
-      <obj_property name="ObjectShortName">i_data_rd_data[31:0]</obj_property>
70 
+   <wvobject fp_name="/e_testbed/system/core/i_instr_data" type="array" db_ref_id="1">
71 
+      <obj_property name="ElementShortName">i_instr_data[31:0]</obj_property>
72 
+      <obj_property name="ObjectShortName">i_instr_data[31:0]</obj_property>
117 73 
       <obj_property name="Radix">HEXRADIX</obj_property>
118 74 
    </wvobject>
119 
-   <wvobject fp_name="/e_testbed/system/core/o_data_rd_en" type="array" db_ref_id="1">
120 
-      <obj_property name="ElementShortName">o_data_rd_en[3:0]</obj_property>
121 
-      <obj_property name="ObjectShortName">o_data_rd_en[3:0]</obj_property>
122 
-   </wvobject>
123 75 
    <wvobject fp_name="/e_testbed/system/eth/o_bm_req" type="logic" db_ref_id="1">
124 76 
       <obj_property name="ElementShortName">o_bm_req</obj_property>
125 77 
       <obj_property name="ObjectShortName">o_bm_req</obj_property>
mips_sys.xise
View file @ 6f152d9
... ... 
@@ -28,7 +28,7 @@
28 28 
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
29 29 
     </file>
30 30 
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
31 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
32 32 
       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
33 33 
     </file>
34 34 
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
... ... 
@@ -52,21 +52,21 @@
52 52 
       <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
53 53 
     </file>
54 54 
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
55 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
56 56 
       <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
57 57 
     </file>
58 58 
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
59 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
60 60 
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
61 61 
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
62 62 
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
63 63 
     </file>
64 64 
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
65 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
66 66 
       <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
67 67 
     </file>
68 68 
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
69 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
70 70 
       <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
71 71 
     </file>
72 72 
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
... ... 
@@ -76,11 +76,11 @@
76 76 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
77 77 
     </file>
78 78 
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
79 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
79 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
80 80 
       <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
81 81 
     </file>
82 82 
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
83 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
83 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
84 84 
       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
85 85 
     </file>
86 86 
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
... ... 
@@ -91,19 +91,19 @@
91 91 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
92 92 
     </file>
93 93 
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
94 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
94 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
95 95 
       <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
96 96 
     </file>
97 97 
     <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
98 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
98 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
99 99 
       <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
100 100 
     </file>
101 101 
     <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
102 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
102 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
103 103 
       <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
104 104 
     </file>
105 105 
     <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
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-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
106 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
107 107 
       <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
108 108 
     </file>
109 109 
     <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
... ... 
@@ -111,21 +111,21 @@
111 111 
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
112 112 
     </file>
113 113 
     <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
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-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
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+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
115 115 
       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
116 116 
     </file>
117 117 
     <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
118 118 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
119 119 
     </file>
120 120 
     <file xil_pn:name="io/uart.vhd" xil_pn:type="FILE_VHDL">
121 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
121 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
122 122 
       <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
123 123 
     </file>
124 124 
     <file xil_pn:name="constraints/uart.ucf" xil_pn:type="FILE_UCF">
125 125 
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
126 126 
     </file>
127 127 
     <file xil_pn:name="blocks/fifo.vhd" xil_pn:type="FILE_VHDL">
128 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
128 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
129 129 
       <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
130 130 
     </file>
131 131 
     <file xil_pn:name="blocks/rwram.vhd" xil_pn:type="FILE_VHDL">
... ... 
@@ -133,15 +133,15 @@
133 133 
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
134 134 
     </file>
135 135 
     <file xil_pn:name="io/eth/eth.vhd" xil_pn:type="FILE_VHDL">
136 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
136 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
137 137 
       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
138 138 
     </file>
139 139 
     <file xil_pn:name="io/eth/rst.vhd" xil_pn:type="FILE_VHDL">
140 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
140 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
141 141 
       <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
142 142 
     </file>
143 143 
     <file xil_pn:name="io/eth/rxif.vhd" xil_pn:type="FILE_VHDL">
144 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
144 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
145 145 
       <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
146 146 
     </file>
147 147 
     <file xil_pn:name="constraints/eth.ucf" xil_pn:type="FILE_UCF">
... ... 
@@ -152,15 +152,15 @@
152 152 
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
153 153 
     </file>
154 154 
     <file xil_pn:name="io/eth/rxframe.vhd" xil_pn:type="FILE_VHDL">
155 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
155 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
156 156 
       <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
157 157 
     </file>
158 158 
     <file xil_pn:name="io/eth/txif.vhd" xil_pn:type="FILE_VHDL">
159 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="206"/>
159 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
160 160 
       <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
161 161 
     </file>
162 162 
     <file xil_pn:name="io/eth/txframe.vhd" xil_pn:type="FILE_VHDL">
163 
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="210"/>
163 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
164 164 
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
165 165 
     </file>
166 166 
   </files>
test/testbed.vhd
View file @ 6f152d9
... ... 
@@ -29,10 +29,38 @@ ARCHITECTURE a_testbed OF e_testbed IS
29 29 
         );
30 30 
     END COMPONENT e_system;
31 31
32 
+    TYPE t_eth_data IS ARRAY(0 TO 160 - 1) OF std_logic_vector(3 DOWNTO 0);
33 
+    CONSTANT eth_data: t_eth_data := (
34 
+        X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"5",
35 
+        X"5", X"5", X"5", X"5", X"5", X"5", X"5", X"D",
36 
+        X"F", X"F", X"F", X"F", X"F", X"F", X"F", X"F",
37 
+        X"F", X"F", X"F", X"F", X"0", X"0", X"D", X"1",
38 
+        X"0", X"6", X"C", X"D", X"5", X"7", X"D", X"2",
39 
+        X"8", X"0", X"0", X"0", X"5", X"4", X"0", X"0",
40 
+        X"0", X"0", X"6", X"3", X"9", X"3", X"E", X"D",
41 
+        X"0", X"4", X"0", X"0", X"0", X"4", X"1", X"1",
42 
+        X"0", X"4", X"7", X"2", X"0", X"C", X"8", X"A",
43 
+        X"0", X"0", X"A", X"0", X"F", X"F", X"F", X"F",
44 
+        X"F", X"F", X"F", X"F", X"7", X"9", X"3", X"5",
45 
+        X"0", X"0", X"1", X"0", X"0", X"0", X"2", X"2",
46 
+        X"B", X"9", X"1", X"D", X"4", X"4", X"9", X"6",
47 
+        X"5", X"6", X"3", X"7", X"0", X"2", X"9", X"6",
48 
+        X"3", X"7", X"4", X"7", X"0", X"2", X"5", X"6",
49 
+        X"9", X"6", X"E", X"6", X"0", X"2", X"C", X"6",
50 
+        X"1", X"6", X"E", X"6", X"7", X"6", X"5", X"6",
51 
+        X"2", X"7", X"0", X"2", X"4", X"5", X"5", X"6",
52 
+        X"3", X"7", X"4", X"7", X"1", X"2", X"A", X"0",
53 
+        X"B", X"A", X"3", X"8", X"D", X"8", X"D", X"1"
54 
+        );
55 
+
32 56 
     SIGNAL s_clk:             std_logic;
57 
+    SIGNAL s_eth_clk:         std_logic;
58 
+    SIGNAL s_eth_rxd:         std_logic_vector(3 DOWNTO 0);
59 
+    SIGNAL s_eth_rx_dv:       std_logic;
33 60 
     SIGNAL pin_leds:          std_logic_vector(7 DOWNTO 0);
34 61 
     SIGNAL pin_lcd:           t_io_lcd_pins;
35 62 
     SIGNAL pin_uart_loopback: std_logic;
63 
+    SIGNAL pin_eth_rxd:       std_logic_vector(4 DOWNTO 0);
36 64 
     SIGNAL pin_eth_txd:       std_logic_vector(3 DOWNTO 0);
37 65 
     SIGNAL pin_eth_tx_en:     std_logic;
38 66
... ... 
@@ -46,26 +74,55 @@ BEGIN
46 74 
             pin_i_switches   => (sw => (OTHERS => '0'), OTHERS => '0'),
47 75 
             pin_i_uart_rx    => pin_uart_loopback,
48 76 
             pin_o_uart_tx    => pin_uart_loopback,
49 
-            pin_i_eth_rx_clk => '0',
50 
-            pin_i_eth_rxd    => "00000",
51 
-            pin_i_eth_rx_dv  => '0',
52 
-            pin_i_eth_crs    => '0',
77 
+            pin_i_eth_rx_clk => s_eth_clk,
78 
+            pin_i_eth_rxd    => pin_eth_rxd,
79 
+            pin_i_eth_rx_dv  => s_eth_rx_dv,
80 
+            pin_i_eth_crs    => s_eth_rx_dv,
53 81 
             pin_i_eth_col    => '0',
54 
-            pin_i_eth_tx_clk => '0',
82 
+            pin_i_eth_tx_clk => s_eth_clk,
55 83 
             pin_o_eth_txd    => pin_eth_txd,
56 84 
             pin_o_eth_tx_en  => pin_eth_tx_en
57 85 
         );
58 86
59 
-    p_rst_clk: PROCESS
87 
+    pin_eth_rxd <= "0" & s_eth_rxd;
88 
+
89 
+    p_clk: PROCESS
60 90 
     BEGIN
61 
-        s_clk <= '0';
62 91 
         WHILE TRUE LOOP
92 
+            s_clk <= '0';
63 93 
             WAIT FOR 10 ns;
64 94 
             s_clk <= '1';
65 95 
             WAIT FOR 10 ns;
66 
-            s_clk <= '0';
67 96 
         END LOOP;
68 
-    END PROCESS p_rst_clk;
97 
+    END PROCESS p_clk;
98 
+
99 
+    p_eth_clk: PROCESS
100 
+    BEGIN
101 
+        WHILE TRUE LOOP
102 
+            s_eth_clk <= '0';
103 
+            WAIT FOR 20 ns;
104 
+            s_eth_clk <= '1';
105 
+            WAIT FOR 20 ns;
106 
+        END LOOP;
107 
+    END PROCESS p_eth_clk;
108 
+
109 
+    p_eth_data: PROCESS
110 
+    BEGIN
111 
+        s_eth_rxd   <= "0000";
112 
+        s_eth_rx_dv <= '0';
113 
+        WAIT FOR 1 ms;
114 
+        WAIT UNTIL s_eth_clk = '1';
115 
+        WAIT UNTIL s_eth_clk = '0';
116 
+        FOR i IN 0 TO eth_data'length - 1 LOOP
117 
+            s_eth_rxd   <= eth_data(i);
118 
+            s_eth_rx_dv <= '1';
119 
+            WAIT UNTIL s_eth_clk = '1';
120 
+            WAIT UNTIL s_eth_clk = '0';
121 
+        END LOOP;
122 
+        s_eth_rxd   <= "0000";
123 
+        s_eth_rx_dv <= '0';
124 
+        WAIT;
125 
+    END PROCESS p_eth_data;
69 126
70 127 
 END ARCHITECTURE a_testbed;
71 128
72 129