MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
| constraints | implemented TX part of UART paripheral | 2012-02-16 20:33:52 |
|---|---|---|
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | implemented TX part of UART paripheral | 2012-02-16 20:33:52 |
| io | implemented TX part of UART paripheral | 2012-02-16 20:33:52 |
| mips | fixed instruction word input on stall, fixed uninitialized instruction word after reset by stalling 1 cycle | 2012-02-16 20:09:51 |
| system | implemented TX part of UART paripheral | 2012-02-16 20:33:52 |
| test | implemented TX part of UART paripheral | 2012-02-16 20:33:52 |
| .gitignore | impact project | 2012-02-11 00:32:06 |
| Default.wcfg | implemented TX part of UART paripheral | 2012-02-16 20:33:52 |
| mips_sys.ipf | impact project | 2012-02-11 00:32:06 |
| mips_sys.xise | implemented TX part of UART paripheral | 2012-02-16 20:33:52 |