changed MIPS core to use read and write ack instead of stall input (4059dff) - mips_sys · BlinkenArea

changed MIPS core to use read and write ack instead of stall input

Stefan Schuermans commited on 2012-02-29 21:28:37
Showing 3 changed files, with 36 additions and 19 deletions.

mips/core.vhd 02c674d..fcd68a9
mips_sys.xise 5897883..cb2aef9
system/system.vhd 347b578..1b51cea

mips/core.vhd

@@ -7,14 +7,15 @@ ENTITY e_mips_core IS
     PORT (
         rst:            IN  std_logic;
         clk:            IN  std_logic;
-        i_stall:        IN  std_logic;
         o_instr_addr:   OUT std_logic_vector(31 DOWNTO 0);
         i_instr_data:   IN  std_logic_vector(31 DOWNTO 0);
         o_data_addr:    OUT std_logic_vector(31 DOWNTO 0);
         i_data_rd_data: IN  std_logic_vector(31 DOWNTO 0);
         o_data_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
+        i_data_rd_ack:  IN  std_logic;
         o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
-        o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0)
+        o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0);
+        i_data_wr_ack:  IN  std_logic
     );
 END ENTITY e_mips_core;
 
@@ -23,6 +24,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
     SIGNAL s_stall:         std_logic;
     SIGNAL r_stall_reset:   std_logic := '1';
     SIGNAL s_stall_data_rd: std_logic;
+    SIGNAL s_stall_data_wr: std_logic;
 
     SIGNAL r_pc:         std_logic_vector(31 DOWNTO 0) := X"FFFFFFFC";
     SIGNAL n_pc:         std_logic_vector(31 DOWNTO 0);
@@ -186,7 +188,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
 
 BEGIN
 
-    s_stall <= i_stall OR r_stall_reset OR s_stall_data_rd OR s_mul_busy OR s_div_busy;
+    s_stall <= r_stall_reset OR s_stall_data_rd OR s_stall_data_wr OR s_mul_busy OR s_div_busy;
 
     decoder: e_mips_decoder
         PORT MAP (
@@ -476,16 +478,16 @@ BEGIN
         END IF;
     END PROCESS p_data_rd_en;
 
-    p_data_rd: PROCESS(r_data_rd, r_op, r_ldst, s_data_addr, r_reg_t, i_data_rd_data, s_val_t)
+    p_data_rd: PROCESS(r_data_rd, r_op, r_ldst, s_data_addr, r_reg_t,
+                       i_data_rd_data, i_data_rd_ack, s_val_t)
+        VARIABLE v_read: boolean;
         VARIABLE v_b:    std_logic_vector( 7 DOWNTO 0);
         VARIABLE v_h:    std_logic_vector(15 DOWNTO 0);
         VARIABLE v_w:    std_logic_vector(31 DOWNTO 0);
     BEGIN
+        v_read          := false;
         s_stall_data_rd <= '0';
         n_data_rd       <= data_rd_idle;
-        s_reg_wr_data_no   <= (OTHERS => '0');
-        s_reg_wr_data_data <= (OTHERS => '0');
-        s_reg_wr_data_en   <= '0';
         CASE r_data_rd IS
             WHEN data_rd_idle =>
                 IF r_op = op_l THEN
@@ -493,6 +495,18 @@ BEGIN
                     n_data_rd       <= data_rd_read;
                 END IF;
             WHEN data_rd_read =>
+                IF i_data_rd_ack = '0' THEN
+                    s_stall_data_rd <= '1';
+                    n_data_rd       <= data_rd_read;
+                ELSE
+                    v_read := true;
+                END IF;
+            WHEN OTHERS => NULL;
+        END CASE;
+        s_reg_wr_data_no   <= (OTHERS => '0');
+        s_reg_wr_data_data <= (OTHERS => '0');
+        s_reg_wr_data_en   <= '0';
+        IF v_read THEN
             CASE r_ldst IS
                 WHEN ldst_b | ldst_bu =>
                     CASE s_data_addr(1 DOWNTO 0) IS
@@ -542,8 +556,7 @@ BEGIN
             END CASE;
             s_reg_wr_data_no <= r_reg_t;
             s_reg_wr_data_en <= '1';
-            WHEN OTHERS => NULL;
-        END CASE;
+        END IF;
     END PROCESS p_data_rd;
 
     p_sync_data_rd: PROCESS(rst, clk)
@@ -551,16 +564,15 @@ BEGIN
         IF rst = '1' THEN
             r_data_rd <= data_rd_idle;
         ELSIF rising_edge(clk) THEN
-            IF i_stall = '0' THEN
             r_data_rd <= n_data_rd;
         END IF;
-        END IF;
     END PROCESS p_sync_data_rd;
 
-    p_data_wr: PROCESS(r_op, r_ldst, s_data_addr, s_val_t)
+    p_data_wr: PROCESS(r_op, r_ldst, s_data_addr, s_val_t, i_data_wr_ack)
     BEGIN
         o_data_wr_data  <= (OTHERS => '0');
         o_data_wr_en    <= "0000";
+        s_stall_data_wr <= '0';
         IF r_op = op_s THEN
             CASE r_ldst IS
                 WHEN ldst_b =>
@@ -626,6 +638,9 @@ BEGIN
                     END CASE;
                 WHEN OTHERS => NULL;
             END CASE;
+            IF i_data_wr_ack = '0' THEN
+                s_stall_data_wr <= '1';
+            END IF;
         END IF;
     END PROCESS p_data_wr;
 
@@ -674,10 +689,10 @@ BEGIN
     END PROCESS p_sync_reg_hi_lo;
 
     s_mul_signed <= '1' WHEN r_op = op_mult ELSE '0';
-    s_mul_start  <= '1' WHEN i_stall = '0' AND (r_op = op_mult OR r_op = op_multu) ELSE '0';
+    s_mul_start  <= '1' WHEN r_op = op_mult OR r_op = op_multu ELSE '0';
 
     s_div_signed <= '1' WHEN r_op = op_div ELSE '0';
-    s_div_start  <= '1' WHEN i_stall = '0' AND (r_op = op_div OR r_op = op_divu) ELSE '0';
+    s_div_start  <= '1' WHEN r_op = op_div OR r_op = op_divu ELSE '0';
 
     p_link: PROCESS(r_pc, r_link)
     BEGIN

mips_sys.xise

View file @ 4059dff

@@ -387,7 +387,7 @@
     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="100 us" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1 ms" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>

system/system.vhd

View file @ 4059dff

@@ -71,14 +71,15 @@ ARCHITECTURE a_system OF e_system IS
         PORT (
             rst:            IN  std_logic;
             clk:            IN  std_logic;
-            i_stall:        IN  std_logic;
             o_instr_addr:   OUT std_logic_vector(31 DOWNTO 0);
             i_instr_data:   IN  std_logic_vector(31 DOWNTO 0);
             o_data_addr:    OUT std_logic_vector(31 DOWNTO 0);
             i_data_rd_data: IN  std_logic_vector(31 DOWNTO 0);
             o_data_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
+            i_data_rd_ack:  IN  std_logic;
             o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
-            o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0)
+            o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0);
+            i_data_wr_ack:  IN  std_logic
         );
     END COMPONENT e_mips_core;
 
@@ -228,14 +229,15 @@ BEGIN
         PORT MAP (
             rst            => rst,
             clk            => clk,
-            i_stall        => '0',
             o_instr_addr   => s_instr_addr,
             i_instr_data   => s_instr_data,
             o_data_addr    => s_dbus_addr,
             i_data_rd_data => s_dbus_rd_data,
             o_data_rd_en   => s_dbus_rd_en,
+            i_data_rd_ack  => '1',
             o_data_wr_data => s_dbus_wr_data,
-            o_data_wr_en   => s_dbus_wr_en
+            o_data_wr_en   => s_dbus_wr_en,
+            i_data_wr_ack  => '1'
         );
 
     instr: e_rom


...	...	@@ -387,7 +387,7 @@
387	387	<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
388	388	<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
389	389	<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
390		- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="100 us" xil_pn:valueState="non-default"/>
	390	+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1 ms" xil_pn:valueState="non-default"/>
391	391	<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
392	392	<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
393	393	<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>

...	...	@@ -71,14 +71,15 @@ ARCHITECTURE a_system OF e_system IS
71	71	PORT (
72	72	rst: IN std_logic;
73	73	clk: IN std_logic;
74		- i_stall: IN std_logic;
75	74	o_instr_addr: OUT std_logic_vector(31 DOWNTO 0);
76	75	i_instr_data: IN std_logic_vector(31 DOWNTO 0);
77	76	o_data_addr: OUT std_logic_vector(31 DOWNTO 0);
78	77	i_data_rd_data: IN std_logic_vector(31 DOWNTO 0);
79	78	o_data_rd_en: OUT std_logic_vector( 3 DOWNTO 0);
	79	+ i_data_rd_ack: IN std_logic;
80	80	o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
81		- o_data_wr_en: OUT std_logic_vector( 3 DOWNTO 0)
	81	+ o_data_wr_en: OUT std_logic_vector( 3 DOWNTO 0);
	82	+ i_data_wr_ack: IN std_logic
82	83	);
83	84	END COMPONENT e_mips_core;
84	85
...	...	@@ -228,14 +229,15 @@ BEGIN
228	229	PORT MAP (
229	230	rst => rst,
230	231	clk => clk,
231		- i_stall => '0',
232	232	o_instr_addr => s_instr_addr,
233	233	i_instr_data => s_instr_data,
234	234	o_data_addr => s_dbus_addr,
235	235	i_data_rd_data => s_dbus_rd_data,
236	236	o_data_rd_en => s_dbus_rd_en,
	237	+ i_data_rd_ack => '1',
237	238	o_data_wr_data => s_dbus_wr_data,
238		- o_data_wr_en => s_dbus_wr_en
	239	+ o_data_wr_en => s_dbus_wr_en,
	240	+ i_data_wr_ack => '1'
239	241	);
240	242
241	243	instr: e_rom
242	244

...	...	@@ -7,14 +7,15 @@ ENTITY e_mips_core IS
7	7	PORT (
8	8	rst: IN std_logic;
9	9	clk: IN std_logic;
10		- i_stall: IN std_logic;
11	10	o_instr_addr: OUT std_logic_vector(31 DOWNTO 0);
12	11	i_instr_data: IN std_logic_vector(31 DOWNTO 0);
13	12	o_data_addr: OUT std_logic_vector(31 DOWNTO 0);
14	13	i_data_rd_data: IN std_logic_vector(31 DOWNTO 0);
15	14	o_data_rd_en: OUT std_logic_vector( 3 DOWNTO 0);
	15	+ i_data_rd_ack: IN std_logic;
16	16	o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
17		- o_data_wr_en: OUT std_logic_vector( 3 DOWNTO 0)
	17	+ o_data_wr_en: OUT std_logic_vector( 3 DOWNTO 0);
	18	+ i_data_wr_ack: IN std_logic
18	19	);
19	20	END ENTITY e_mips_core;
20	21
...	...	@@ -23,6 +24,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
23	24	SIGNAL s_stall: std_logic;
24	25	SIGNAL r_stall_reset: std_logic := '1';
25	26	SIGNAL s_stall_data_rd: std_logic;
	27	+ SIGNAL s_stall_data_wr: std_logic;
26	28
27	29	SIGNAL r_pc: std_logic_vector(31 DOWNTO 0) := X"FFFFFFFC";
28	30	SIGNAL n_pc: std_logic_vector(31 DOWNTO 0);
...	...	@@ -186,7 +188,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
186	188
187	189	BEGIN
188	190
189		- s_stall <= i_stall OR r_stall_reset OR s_stall_data_rd OR s_mul_busy OR s_div_busy;
	191	+ s_stall <= r_stall_reset OR s_stall_data_rd OR s_stall_data_wr OR s_mul_busy OR s_div_busy;
190	192
191	193	decoder: e_mips_decoder
192	194	PORT MAP (
...	...	@@ -476,16 +478,16 @@ BEGIN
476	478	END IF;
477	479	END PROCESS p_data_rd_en;
478	480
479		- p_data_rd: PROCESS(r_data_rd, r_op, r_ldst, s_data_addr, r_reg_t, i_data_rd_data, s_val_t)
	481	+ p_data_rd: PROCESS(r_data_rd, r_op, r_ldst, s_data_addr, r_reg_t,
	482	+ i_data_rd_data, i_data_rd_ack, s_val_t)
	483	+ VARIABLE v_read: boolean;
480	484	VARIABLE v_b: std_logic_vector( 7 DOWNTO 0);
481	485	VARIABLE v_h: std_logic_vector(15 DOWNTO 0);
482	486	VARIABLE v_w: std_logic_vector(31 DOWNTO 0);
483	487	BEGIN
	488	+ v_read := false;
484	489	s_stall_data_rd <= '0';
485	490	n_data_rd <= data_rd_idle;
486		- s_reg_wr_data_no <= (OTHERS => '0');
487		- s_reg_wr_data_data <= (OTHERS => '0');
488		- s_reg_wr_data_en <= '0';
489	491	CASE r_data_rd IS
490	492	WHEN data_rd_idle =>
491	493	IF r_op = op_l THEN
...	...	@@ -493,6 +495,18 @@ BEGIN
493	495	n_data_rd <= data_rd_read;
494	496	END IF;
495	497	WHEN data_rd_read =>
	498	+ IF i_data_rd_ack = '0' THEN
	499	+ s_stall_data_rd <= '1';
	500	+ n_data_rd <= data_rd_read;
	501	+ ELSE
	502	+ v_read := true;
	503	+ END IF;
	504	+ WHEN OTHERS => NULL;
	505	+ END CASE;
	506	+ s_reg_wr_data_no <= (OTHERS => '0');
	507	+ s_reg_wr_data_data <= (OTHERS => '0');
	508	+ s_reg_wr_data_en <= '0';
	509	+ IF v_read THEN
496	510	CASE r_ldst IS
497	511	WHEN ldst_b \| ldst_bu =>
498	512	CASE s_data_addr(1 DOWNTO 0) IS
...	...	@@ -542,8 +556,7 @@ BEGIN
542	556	END CASE;
543	557	s_reg_wr_data_no <= r_reg_t;
544	558	s_reg_wr_data_en <= '1';
545		- WHEN OTHERS => NULL;
546		- END CASE;
	559	+ END IF;
547	560	END PROCESS p_data_rd;
548	561
549	562	p_sync_data_rd: PROCESS(rst, clk)
...	...	@@ -551,16 +564,15 @@ BEGIN
551	564	IF rst = '1' THEN
552	565	r_data_rd <= data_rd_idle;
553	566	ELSIF rising_edge(clk) THEN
554		- IF i_stall = '0' THEN
555	567	r_data_rd <= n_data_rd;
556	568	END IF;
557		- END IF;
558	569	END PROCESS p_sync_data_rd;
559	570
560		- p_data_wr: PROCESS(r_op, r_ldst, s_data_addr, s_val_t)
	571	+ p_data_wr: PROCESS(r_op, r_ldst, s_data_addr, s_val_t, i_data_wr_ack)
561	572	BEGIN
562	573	o_data_wr_data <= (OTHERS => '0');
563	574	o_data_wr_en <= "0000";
	575	+ s_stall_data_wr <= '0';
564	576	IF r_op = op_s THEN
565	577	CASE r_ldst IS
566	578	WHEN ldst_b =>
...	...	@@ -626,6 +638,9 @@ BEGIN
626	638	END CASE;
627	639	WHEN OTHERS => NULL;
628	640	END CASE;
	641	+ IF i_data_wr_ack = '0' THEN
	642	+ s_stall_data_wr <= '1';
	643	+ END IF;
629	644	END IF;
630	645	END PROCESS p_data_wr;
631	646
...	...	@@ -674,10 +689,10 @@ BEGIN
674	689	END PROCESS p_sync_reg_hi_lo;
675	690
676	691	s_mul_signed <= '1' WHEN r_op = op_mult ELSE '0';
677		- s_mul_start <= '1' WHEN i_stall = '0' AND (r_op = op_mult OR r_op = op_multu) ELSE '0';
	692	+ s_mul_start <= '1' WHEN r_op = op_mult OR r_op = op_multu ELSE '0';
678	693
679	694	s_div_signed <= '1' WHEN r_op = op_div ELSE '0';
680		- s_div_start <= '1' WHEN i_stall = '0' AND (r_op = op_div OR r_op = op_divu) ELSE '0';
	695	+ s_div_start <= '1' WHEN r_op = op_div OR r_op = op_divu ELSE '0';
681	696
682	697	p_link: PROCESS(r_pc, r_link)
683	698	BEGIN