-
implemented ethernet TX interface (not tested yet)
Stefan Schuermans authored on 2012-03-04 21:38:35
-
implemented ethernet RX busmaster -> packet reception working
Stefan Schuermans authored on 2012-03-03 23:42:55
-
converted core to use req and grant signals to access data bus
Stefan Schuermans authored on 2012-03-01 21:23:47
-
changed MIPS core to use read and write ack instead of stall input
Stefan Schuermans authored on 2012-02-29 21:28:37
-
shortcut to switch between HW and simulation config
Stefan Schuermans authored on 2012-02-29 21:28:34
-
add read_enable signal to data bus and some peripherals
Stefan Schuermans authored on 2012-02-26 21:20:53
-
fix reading (1 cycle latency) from ethernet peripheral
Stefan Schuermans authored on 2012-02-26 18:26:02
-
removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy
Stefan Schuermans authored on 2012-02-21 20:40:30
-
begin of ethernet RX implementation, so far only test interface to core, does not meet timing
Stefan Schuermans authored on 2012-02-20 21:16:03
-
increased code and data address range to 8KB
Stefan Schuermans authored on 2012-02-20 15:55:19
-
fixed instruction word input on stall, fixed uninitialized instruction word after reset by stalling 1 cycle
Stefan Schuermans authored on 2012-02-16 20:09:51
-
implemented displaying rotary counter (octal)
Stefan Schuermans authored on 2012-02-12 21:51:32
-
read peripherals with one cycle delay - as for memory
Stefan Schuermans authored on 2012-02-12 19:10:11
-
converted code to use constants in data memory
Stefan Schuermans authored on 2012-02-12 18:24:53
-
implemented loading of data memory from firmware
Stefan Schuermans authored on 2012-02-12 17:47:50
-
slower LED animation for execution on FPGA
Stefan Schuermans authored on 2012-02-11 00:31:59
-
clock and reset constraints are for whole system
Stefan Schuermans authored on 2012-02-10 23:22:30