mips_sys

@@ -20,11 +20,12 @@ END ENTITY e_mips_core;

 ARCHITECTURE a_mips_core OF e_mips_core IS

     SIGNAL s_stall:         std_logic;

+    SIGNAL r_stall_reset:   std_logic := '1';

     SIGNAL s_stall_data_rd: std_logic;

     SIGNAL r_pc:         std_logic_vector(31 DOWNTO 0) := X"FFFFFFFC";

     SIGNAL n_pc:         std_logic_vector(31 DOWNTO 0);

-

+    SIGNAL r_instr_data: std_logic_vector(31 DOWNTO 0) := X"00000000";

     SIGNAL s_instr:      std_logic_vector(31 DOWNTO 0);

     SIGNAL n_reg_s:  std_logic_vector( 4 DOWNTO 0);

@@ -184,7 +185,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS

 BEGIN

-    s_stall <= i_stall OR s_stall_data_rd OR s_mul_busy OR s_div_busy;

+    s_stall <= i_stall OR r_stall_reset OR s_stall_data_rd OR s_mul_busy OR s_div_busy;

     decoder: e_mips_decoder

         PORT MAP (

@@ -259,22 +260,27 @@ BEGIN

     p_sync_pc: PROCESS(rst, clk)

     BEGIN

         IF rst = '1' THEN

+            r_stall_reset <= '1';

             r_pc          <= X"FFFFFFFC";

+            r_instr_data  <= X"00000000";

         ELSIF rising_edge(clk) THEN

+            r_stall_reset <= '0';

             IF s_stall = '0' THEN

                 r_pc         <= n_pc;

+                r_instr_data <= i_instr_data;

             END IF;

         END IF;

     END PROCESS p_sync_pc;

-    p_fetch: PROCESS(s_stall, r_pc, n_pc, i_instr_data)

+    p_fetch: PROCESS(s_stall, r_pc, n_pc, r_instr_data, i_instr_data)

     BEGIN

         IF s_stall = '1' THEN

             o_instr_addr <= r_pc;

+            s_instr      <= r_instr_data;

         ELSE

             o_instr_addr <= n_pc;

-        END IF;

             s_instr      <= i_instr_data;

+        END IF;

     END PROCESS p_fetch;

     p_sync_dec2ex: PROCESS(rst, clk)