fix reading (1 cycle latency) from ethernet peripheral
Stefan Schuermans

Stefan Schuermans commited on 2012-02-26 18:26:02
Showing 1 changed files, with 16 additions and 6 deletions.

... ...
@@ -134,20 +134,30 @@ BEGIN
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         );
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     -- so far only for testing
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-    p_rx_test: PROCESS (i_addr, i_wr_data, i_wr_en,
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-                        s_rx_fifo_rd_rdy, s_rx_fifo_rd_data)
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+    p_rx_test_wr: PROCESS (i_addr, i_wr_data, i_wr_en)
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     BEGIN
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-        o_rd_data       <= X"00000000";
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         s_rx_fifo_rd_en <= '0';
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+        IF i_addr = "01" THEN
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+            IF i_wr_en(0) = '1' THEN
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+                s_rx_fifo_rd_en <= '1';
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+            END IF;
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+        END IF;
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+    END PROCESS p_rx_test_wr;
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+
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+    -- so far only for testing
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+    p_rx_test_rd: PROCESS (rst, clk)
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+    BEGIN
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+        IF rst = '1' THEN
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+            o_rd_data       <= X"00000000";
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+        ELSIF rising_edge(clk) THEN
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+            o_rd_data       <= X"00000000";
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             IF i_addr = "00" THEN
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                 o_rd_data(0) <= s_rx_fifo_rd_rdy;
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             ELSIF i_addr = "01" THEN
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                 o_rd_data(7 DOWNTO 0) <= s_rx_fifo_rd_data;
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-            IF i_wr_en(0) = '1' THEN
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-                s_rx_fifo_rd_en <= '1';
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             END IF;
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         END IF;
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-    END PROCESS p_rx_test;
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+    END PROCESS p_rx_test_rd;
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     pin_o_txd   <= "0000";
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     pin_o_tx_en <= '0';
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