MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
shortcut to switch between HW and simulation config
c559f2f @ 2012-02-29 21:28:34
| blocks | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |
|---|---|---|
| constraints | timing for ethernet clocks | 2012-02-21 21:39:56 |
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | shortcut to switch between HW and simulation config | 2012-02-29 21:28:34 |
| io | add read_enable signal to data bus and some peripherals | 2012-02-26 21:20:53 |
| mips | add read_enable signal to data bus and some peripherals | 2012-02-26 21:20:53 |
| system | add read_enable signal to data bus and some peripherals | 2012-02-26 21:20:53 |
| test | begin of ethernet RX implementation, so far only test interface to core, does not meet timing | 2012-02-20 21:16:03 |
| .gitignore | impact project | 2012-02-11 00:32:06 |
| Default.wcfg | implemented RX part of UART peripheral | 2012-02-20 11:50:59 |
| mips_sys.ipf | impact project | 2012-02-11 00:32:06 |
| mips_sys.xise | removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy | 2012-02-21 20:40:30 |