mips_sys

implemented multi-master feature for data bus extended ethernet block to have busmaster signals (dummy functionality up to now)
Parent 77114e6
Stefan Schuermans

Stefan Schuermans commited on 2012-03-01 21:24:14
Showing 3 changed files, with 177 additions and 33 deletions.

Default.wcfg
View file @ 12f75e0
... ... 
@@ -15,7 +15,7 @@
15 15 
          </top_modules>
16 16 
       </db_ref>
17 17 
    </db_ref_list>
18 
-   <WVObjectSize size="15" />
18 
+   <WVObjectSize size="28" />
19 19 
    <wvobject fp_name="/e_testbed/s_clk" type="logic" db_ref_id="1">
20 20 
       <obj_property name="ElementShortName">s_clk</obj_property>
21 21 
       <obj_property name="ObjectShortName">s_clk</obj_property>
... ... 
@@ -55,32 +55,80 @@
55 55 
       <obj_property name="ElementShortName">s_stall</obj_property>
56 56 
       <obj_property name="ObjectShortName">s_stall</obj_property>
57 57 
    </wvobject>
58 
-   <wvobject fp_name="/e_testbed/system/uart/r_rx_data" type="array" db_ref_id="1">
59 
-      <obj_property name="ElementShortName">r_rx_data[15:0]</obj_property>
60 
-      <obj_property name="ObjectShortName">r_rx_data[15:0]</obj_property>
61 
-      <obj_property name="Radix">HEXRADIX</obj_property>
58 
+   <wvobject fp_name="/e_testbed/system/s_core_req" type="logic" db_ref_id="1">
59 
+      <obj_property name="ElementShortName">s_core_req</obj_property>
60 
+      <obj_property name="ObjectShortName">s_core_req</obj_property>
61 
+   </wvobject>
62 
+   <wvobject fp_name="/e_testbed/system/s_core_grant" type="logic" db_ref_id="1">
63 
+      <obj_property name="ElementShortName">s_core_grant</obj_property>
64 
+      <obj_property name="ObjectShortName">s_core_grant</obj_property>
65 
+   </wvobject>
66 
+   <wvobject fp_name="/e_testbed/system/s_core_addr" type="array" db_ref_id="1">
67 
+      <obj_property name="ElementShortName">s_core_addr[31:0]</obj_property>
68 
+      <obj_property name="ObjectShortName">s_core_addr[31:0]</obj_property>
69 
+   </wvobject>
70 
+   <wvobject fp_name="/e_testbed/system/s_core_rd_data" type="array" db_ref_id="1">
71 
+      <obj_property name="ElementShortName">s_core_rd_data[31:0]</obj_property>
72 
+      <obj_property name="ObjectShortName">s_core_rd_data[31:0]</obj_property>
73 
+   </wvobject>
74 
+   <wvobject fp_name="/e_testbed/system/s_core_rd_en" type="array" db_ref_id="1">
75 
+      <obj_property name="ElementShortName">s_core_rd_en[3:0]</obj_property>
76 
+      <obj_property name="ObjectShortName">s_core_rd_en[3:0]</obj_property>
77 
+   </wvobject>
78 
+   <wvobject fp_name="/e_testbed/system/s_core_wr_data" type="array" db_ref_id="1">
79 
+      <obj_property name="ElementShortName">s_core_wr_data[31:0]</obj_property>
80 
+      <obj_property name="ObjectShortName">s_core_wr_data[31:0]</obj_property>
81 
+   </wvobject>
82 
+   <wvobject fp_name="/e_testbed/system/s_core_wr_en" type="array" db_ref_id="1">
83 
+      <obj_property name="ElementShortName">s_core_wr_en[3:0]</obj_property>
84 
+      <obj_property name="ObjectShortName">s_core_wr_en[3:0]</obj_property>
85 
+   </wvobject>
86 
+   <wvobject fp_name="/e_testbed/system/s_ethbm_req" type="logic" db_ref_id="1">
87 
+      <obj_property name="ElementShortName">s_ethbm_req</obj_property>
88 
+      <obj_property name="ObjectShortName">s_ethbm_req</obj_property>
89 
+   </wvobject>
90 
+   <wvobject fp_name="/e_testbed/system/s_ethbm_grant" type="logic" db_ref_id="1">
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+      <obj_property name="ElementShortName">s_ethbm_grant</obj_property>
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+      <obj_property name="ObjectShortName">s_ethbm_grant</obj_property>
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+   </wvobject>
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+   <wvobject fp_name="/e_testbed/system/s_ethbm_addr" type="array" db_ref_id="1">
95 
+      <obj_property name="ElementShortName">s_ethbm_addr[31:0]</obj_property>
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+      <obj_property name="ObjectShortName">s_ethbm_addr[31:0]</obj_property>
97 
+   </wvobject>
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+   <wvobject fp_name="/e_testbed/system/s_ethbm_rd_data" type="array" db_ref_id="1">
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+      <obj_property name="ElementShortName">s_ethbm_rd_data[31:0]</obj_property>
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+      <obj_property name="ObjectShortName">s_ethbm_rd_data[31:0]</obj_property>
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+   </wvobject>
102 
+   <wvobject fp_name="/e_testbed/system/s_ethbm_rd_en" type="array" db_ref_id="1">
103 
+      <obj_property name="ElementShortName">s_ethbm_rd_en[3:0]</obj_property>
104 
+      <obj_property name="ObjectShortName">s_ethbm_rd_en[3:0]</obj_property>
105 
+   </wvobject>
106 
+   <wvobject fp_name="/e_testbed/system/s_ethbm_wr_data" type="array" db_ref_id="1">
107 
+      <obj_property name="ElementShortName">s_ethbm_wr_data[31:0]</obj_property>
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+      <obj_property name="ObjectShortName">s_ethbm_wr_data[31:0]</obj_property>
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+   </wvobject>
110 
+   <wvobject fp_name="/e_testbed/system/s_ethbm_wr_en" type="array" db_ref_id="1">
111 
+      <obj_property name="ElementShortName">s_ethbm_wr_en[3:0]</obj_property>
112 
+      <obj_property name="ObjectShortName">s_ethbm_wr_en[3:0]</obj_property>
62 113 
    </wvobject>
63 
-   <wvobject fp_name="/e_testbed/system/uart/r_rx_samples" type="array" db_ref_id="1">
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-      <obj_property name="ElementShortName">r_rx_samples[1:0]</obj_property>
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-      <obj_property name="ObjectShortName">r_rx_samples[1:0]</obj_property>
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-      <obj_property name="Radix">BINARYRADIX</obj_property>
114 
+   <wvobject fp_name="/e_testbed/system/s_dbus_addr" type="array" db_ref_id="1">
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+      <obj_property name="ElementShortName">s_dbus_addr[31:0]</obj_property>
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+      <obj_property name="ObjectShortName">s_dbus_addr[31:0]</obj_property>
67 117 
    </wvobject>
68 
-   <wvobject fp_name="/e_testbed/system/uart/r_rx_bit" type="other" db_ref_id="1">
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-      <obj_property name="ElementShortName">r_rx_bit</obj_property>
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-      <obj_property name="ObjectShortName">r_rx_bit</obj_property>
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+   <wvobject fp_name="/e_testbed/system/s_dbus_rd_data" type="array" db_ref_id="1">
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+      <obj_property name="ElementShortName">s_dbus_rd_data[31:0]</obj_property>
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+      <obj_property name="ObjectShortName">s_dbus_rd_data[31:0]</obj_property>
71 121 
    </wvobject>
72 
-   <wvobject fp_name="/e_testbed/system/uart/r_rx_sample" type="other" db_ref_id="1">
73 
-      <obj_property name="DisplayName">label</obj_property>
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-      <obj_property name="ElementShortName">r_rx_sample</obj_property>
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-      <obj_property name="ObjectShortName">r_rx_sample</obj_property>
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-      <obj_property name="label">r_rx_sample</obj_property>
122 
+   <wvobject fp_name="/e_testbed/system/s_dbus_rd_en" type="array" db_ref_id="1">
123 
+      <obj_property name="ElementShortName">s_dbus_rd_en[3:0]</obj_property>
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+      <obj_property name="ObjectShortName">s_dbus_rd_en[3:0]</obj_property>
77 125 
    </wvobject>
78 
-   <wvobject fp_name="/e_testbed/system/uart/r_rx_cnt" type="other" db_ref_id="1">
79 
-      <obj_property name="ElementShortName">r_rx_cnt</obj_property>
80 
-      <obj_property name="ObjectShortName">r_rx_cnt</obj_property>
126 
+   <wvobject fp_name="/e_testbed/system/s_dbus_wr_data" type="array" db_ref_id="1">
127 
+      <obj_property name="ElementShortName">s_dbus_wr_data[31:0]</obj_property>
128 
+      <obj_property name="ObjectShortName">s_dbus_wr_data[31:0]</obj_property>
81 129 
    </wvobject>
82 
-   <wvobject fp_name="/e_testbed/system/uart/r_rx_state" type="other" db_ref_id="1">
83 
-      <obj_property name="ElementShortName">r_rx_state</obj_property>
84 
-      <obj_property name="ObjectShortName">r_rx_state</obj_property>
130 
+   <wvobject fp_name="/e_testbed/system/s_dbus_wr_en" type="array" db_ref_id="1">
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+      <obj_property name="ElementShortName">s_dbus_wr_en[3:0]</obj_property>
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+      <obj_property name="ObjectShortName">s_dbus_wr_en[3:0]</obj_property>
85 133 
    </wvobject>
86 134 
 </wave_config>
io/eth/eth.vhd
View file @ 12f75e0
... ... 
@@ -11,6 +11,13 @@ ENTITY e_io_eth IS
11 11 
         i_rd_en:      IN  std_logic_vector( 3 DOWNTO 0);
12 12 
         i_wr_data:    IN  std_logic_vector(31 DOWNTO 0);
13 13 
         i_wr_en:      IN  std_logic_vector( 3 DOWNTO 0);
14 
+        o_bm_req:     OUT std_logic;
15 
+        i_bm_grant:   IN  std_logic;
16 
+        o_bm_addr:    OUT std_logic_vector(31 DOWNTO 0);
17 
+        i_bm_rd_data: IN  std_logic_vector(31 DOWNTO 0);
18 
+        o_bm_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
19 
+        o_bm_wr_data: OUT std_logic_vector(31 DOWNTO 0);
20 
+        o_bm_wr_en:   OUT std_logic_vector( 3 DOWNTO 0);
14 21 
         pin_o_nrst:   OUT std_logic;
15 22 
         pin_i_rx_clk: IN  std_logic;
16 23 
         pin_i_rxd:    IN  std_logic_vector(4 DOWNTO 0);
... ... 
@@ -80,6 +87,8 @@ ARCHITECTURE a_io_eth OF e_io_eth IS
80 87 
         );
81 88 
     END COMPONENT e_block_fifo;
82 89
90 
+    SIGNAL r_cnt: natural := 0;
91 
+
83 92 
 BEGIN
84 93
85 94 
     reset: e_io_eth_rst
... ... 
@@ -155,5 +164,26 @@ BEGIN
155 164 
     pin_o_txd   <= "0000";
156 165 
     pin_o_tx_en <= '0';
157 166
167 
+    -- bus master: bullshit for now
168 
+    p_bm: PROCESS(rst, clk)
169 
+    BEGIN
170 
+        IF rst = '1' THEN
171 
+            r_cnt <= 0;
172 
+        ELSIF rising_edge(clk) THEN
173 
+            IF r_cnt < 3 THEN
174 
+                r_cnt <= r_cnt + 1;
175 
+            ELSE
176 
+                r_cnt <= 0;
177 
+            END IF;
178 
+        END IF;
179 
+    END PROCESS p_bm;
180 
+
181 
+    -- bus master: bullshit for now
182 
+    o_bm_req     <= '1' WHEN r_cnt = 0 ELSE '0';
183 
+    o_bm_addr    <= (OTHERS => '0');
184 
+    o_bm_rd_en   <= (OTHERS => '0');
185 
+    o_bm_wr_data <= (OTHERS => '0');
186 
+    o_bm_wr_en   <= (OTHERS => '0');
187 
+
158 188 
 END ARCHITECTURE a_io_eth;
159 189
system/system.vhd
View file @ 12f75e0
... ... 
@@ -33,6 +33,22 @@ ARCHITECTURE a_system OF e_system IS
33 33
34 34 
     SIGNAL s_instr_addr:   std_logic_vector(31 DOWNTO 0);
35 35 
     SIGNAL s_instr_data:   std_logic_vector(31 DOWNTO 0);
36 
+
37 
+    SIGNAL s_core_req:     std_logic;
38 
+    SIGNAL s_core_grant:   std_logic;
39 
+    SIGNAL s_core_addr:    std_logic_vector(31 DOWNTO 0);
40 
+    SIGNAL s_core_rd_data: std_logic_vector(31 DOWNTO 0);
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+    SIGNAL s_core_rd_en:   std_logic_vector( 3 DOWNTO 0);
42 
+    SIGNAL s_core_wr_data: std_logic_vector(31 DOWNTO 0);
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+    SIGNAL s_core_wr_en:   std_logic_vector( 3 DOWNTO 0);
44 
+    SIGNAL s_ethbm_req:     std_logic;
45 
+    SIGNAL s_ethbm_grant:   std_logic;
46 
+    SIGNAL s_ethbm_addr:    std_logic_vector(31 DOWNTO 0);
47 
+    SIGNAL s_ethbm_rd_data: std_logic_vector(31 DOWNTO 0);
48 
+    SIGNAL s_ethbm_rd_en:   std_logic_vector( 3 DOWNTO 0);
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+    SIGNAL s_ethbm_wr_data: std_logic_vector(31 DOWNTO 0);
50 
+    SIGNAL s_ethbm_wr_en:   std_logic_vector( 3 DOWNTO 0);
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+
36 52 
     SIGNAL s_dbus_addr:    std_logic_vector(31 DOWNTO 0);
37 53 
     SIGNAL s_dbus_rd_data: std_logic_vector(31 DOWNTO 0);
38 54 
     SIGNAL s_dbus_rd_en:   std_logic_vector( 3 DOWNTO 0);
... ... 
@@ -73,13 +89,13 @@ ARCHITECTURE a_system OF e_system IS
73 89 
             clk:            IN  std_logic;
74 90 
             o_instr_addr:   OUT std_logic_vector(31 DOWNTO 0);
75 91 
             i_instr_data:   IN  std_logic_vector(31 DOWNTO 0);
92 
+            o_data_req:     OUT std_logic;
93 
+            i_data_grant:   IN  std_logic;
76 94 
             o_data_addr:    OUT std_logic_vector(31 DOWNTO 0);
77 95 
             i_data_rd_data: IN  std_logic_vector(31 DOWNTO 0);
78 96 
             o_data_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
79 
-            i_data_rd_ack:  IN  std_logic;
80 97 
             o_data_wr_data: OUT std_logic_vector(31 DOWNTO 0);
81 
-            o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0);
82 
-            i_data_wr_ack:  IN  std_logic
98 
+            o_data_wr_en:   OUT std_logic_vector( 3 DOWNTO 0)
83 99 
         );
84 100 
     END COMPONENT e_mips_core;
85 101
... ... 
@@ -201,6 +217,13 @@ ARCHITECTURE a_system OF e_system IS
201 217 
             i_rd_en:      IN  std_logic_vector( 3 DOWNTO 0);
202 218 
             i_wr_data:    IN  std_logic_vector(31 DOWNTO 0);
203 219 
             i_wr_en:      IN  std_logic_vector( 3 DOWNTO 0);
220 
+            o_bm_req:     OUT std_logic;
221 
+            i_bm_grant:   IN  std_logic;
222 
+            o_bm_addr:    OUT std_logic_vector(31 DOWNTO 0);
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+            i_bm_rd_data: IN  std_logic_vector(31 DOWNTO 0);
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+            o_bm_rd_en:   OUT std_logic_vector( 3 DOWNTO 0);
225 
+            o_bm_wr_data: OUT std_logic_vector(31 DOWNTO 0);
226 
+            o_bm_wr_en:   OUT std_logic_vector( 3 DOWNTO 0);
204 227 
             pin_o_nrst:   OUT std_logic;
205 228 
             pin_i_rx_clk: IN  std_logic;
206 229 
             pin_i_rxd:    IN  std_logic_vector(4 DOWNTO 0);
... ... 
@@ -231,13 +254,13 @@ BEGIN
231 254 
             clk            => clk,
232 255 
             o_instr_addr   => s_instr_addr,
233 256 
             i_instr_data   => s_instr_data,
234 
-            o_data_addr    => s_dbus_addr,
235 
-            i_data_rd_data => s_dbus_rd_data,
236 
-            o_data_rd_en   => s_dbus_rd_en,
237 
-            i_data_rd_ack  => '1',
238 
-            o_data_wr_data => s_dbus_wr_data,
239 
-            o_data_wr_en   => s_dbus_wr_en,
240 
-            i_data_wr_ack  => '1'
257 
+            o_data_req     => s_core_req,
258 
+            i_data_grant   => s_core_grant,
259 
+            o_data_addr    => s_core_addr,
260 
+            i_data_rd_data => s_core_rd_data,
261 
+            o_data_rd_en   => s_core_rd_en,
262 
+            o_data_wr_data => s_core_wr_data,
263 
+            o_data_wr_en   => s_core_wr_en
241 264 
         );
242 265
243 266 
     instr: e_rom
... ... 
@@ -250,6 +273,42 @@ BEGIN
250 273 
             o_data => s_instr_data
251 274 
         );
252 275
276 
+    p_dbus_arbit: PROCESS(s_ethbm_req, s_core_req)
277 
+    BEGIN
278 
+        s_ethbm_grant <= '0';
279 
+        s_core_grant  <= '0';
280 
+        IF s_ethbm_req = '1' THEN
281 
+            s_ethbm_grant <= '1';
282 
+        ELSIF s_core_req = '1' THEN
283 
+            s_core_grant <= '1';
284 
+        END IF;
285 
+    END PROCESS p_dbus_arbit;
286 
+
287 
+    p_dbus_arbit_wr: PROCESS(s_ethbm_grant, s_ethbm_addr, s_ethbm_rd_en,
288 
+                                            s_ethbm_wr_data, s_ethbm_wr_en,
289 
+                             s_core_grant, s_core_addr, s_core_rd_en,
290 
+                                           s_core_wr_data, s_core_wr_en)
291 
+    BEGIN
292 
+        s_dbus_addr    <= (OTHERS => '0');
293 
+        s_dbus_rd_en   <= (OTHERS => '0');
294 
+        s_dbus_wr_data <= (OTHERS => '0');
295 
+        s_dbus_wr_en   <= (OTHERS => '0');
296 
+        IF s_ethbm_grant = '1' THEN
297 
+            s_dbus_addr    <= s_ethbm_addr;
298 
+            s_dbus_rd_en   <= s_ethbm_rd_en;
299 
+            s_dbus_wr_data <= s_ethbm_wr_data;
300 
+            s_dbus_wr_en   <= s_ethbm_wr_en;
301 
+        ELSIF s_core_grant = '1' THEN
302 
+            s_dbus_addr    <= s_core_addr;
303 
+            s_dbus_rd_en   <= s_core_rd_en;
304 
+            s_dbus_wr_data <= s_core_wr_data;
305 
+            s_dbus_wr_en   <= s_core_wr_en;
306 
+        END IF;
307 
+    END PROCESS p_dbus_arbit_wr;
308 
+
309 
+    s_ethbm_rd_data <= s_dbus_rd_data;
310 
+    s_core_rd_data  <= s_dbus_rd_data;
311 
+
253 312 
     p_dbus_rd_sync: PROCESS(rst, clk)
254 313 
     BEGIN
255 314 
         IF rst = '1' THEN
... ... 
@@ -445,6 +504,13 @@ BEGIN
445 504 
             i_rd_en      => s_eth_rd_en,
446 505 
             i_wr_data    => s_eth_wr_data,
447 506 
             i_wr_en      => s_eth_wr_en,
507 
+            o_bm_req     => s_ethbm_req,
508 
+            i_bm_grant   => s_ethbm_grant,
509 
+            o_bm_addr    => s_ethbm_addr,
510 
+            i_bm_rd_data => s_ethbm_rd_data,
511 
+            o_bm_rd_en   => s_ethbm_rd_en,
512 
+            o_bm_wr_data => s_ethbm_wr_data,
513 
+            o_bm_wr_en   => s_ethbm_wr_en,
448 514 
             pin_o_nrst   => pin_o_eth_nrst,
449 515 
             pin_i_rx_clk => pin_i_eth_rx_clk,
450 516 
             pin_i_rxd    => pin_i_eth_rxd,
451 517