implemented RX part of UART peripheral
Stefan Schuermans commited on 2012-02-20 11:50:59
Showing 6 changed files, with 210 additions and 86 deletions.
- Default.wcfg f51e3f9..041bf43
- constraints/uart.ucf 46f41b4..c2180a9
- fw/main.c 1cb04ac..cd95816
- io/uart.vhd 568a020..1be07e2
- system/system.vhd a0d75fa..6e50e7e
- test/testbed.vhd 66e62b5..165803f
| ... | ... |
@@ -15,7 +15,7 @@ |
| 15 | 15 |
</top_modules> |
| 16 | 16 |
</db_ref> |
| 17 | 17 |
</db_ref_list> |
| 18 |
- <WVObjectSize size="26" /> |
|
| 18 |
+ <WVObjectSize size="15" /> |
|
| 19 | 19 |
<wvobject fp_name="/e_testbed/s_clk" type="logic" db_ref_id="1"> |
| 20 | 20 |
<obj_property name="ElementShortName">s_clk</obj_property> |
| 21 | 21 |
<obj_property name="ObjectShortName">s_clk</obj_property> |
| ... | ... |
@@ -28,35 +28,19 @@ |
| 28 | 28 |
<obj_property name="ElementShortName">pin_lcd</obj_property> |
| 29 | 29 |
<obj_property name="ObjectShortName">pin_lcd</obj_property> |
| 30 | 30 |
</wvobject> |
| 31 |
- <wvobject fp_name="/e_testbed/pin_uart_tx" type="logic" db_ref_id="1"> |
|
| 32 |
- <obj_property name="ElementShortName">pin_uart_tx</obj_property> |
|
| 33 |
- <obj_property name="ObjectShortName">pin_uart_tx</obj_property> |
|
| 31 |
+ <wvobject fp_name="/e_testbed/system/pin_i_uart_rx" type="logic" db_ref_id="1"> |
|
| 32 |
+ <obj_property name="ElementShortName">pin_i_uart_rx</obj_property> |
|
| 33 |
+ <obj_property name="ObjectShortName">pin_i_uart_rx</obj_property> |
|
| 34 |
+ </wvobject> |
|
| 35 |
+ <wvobject fp_name="/e_testbed/system/pin_o_uart_tx" type="logic" db_ref_id="1"> |
|
| 36 |
+ <obj_property name="ElementShortName">pin_o_uart_tx</obj_property> |
|
| 37 |
+ <obj_property name="ObjectShortName">pin_o_uart_tx</obj_property> |
|
| 34 | 38 |
</wvobject> |
| 35 | 39 |
<wvobject fp_name="/e_testbed/system/core/regs/r_regs[29]" type="array" db_ref_id="1"> |
| 36 | 40 |
<obj_property name="ElementShortName">[29]</obj_property> |
| 37 | 41 |
<obj_property name="ObjectShortName">r_regs[29]</obj_property> |
| 38 | 42 |
<obj_property name="Radix">HEXRADIX</obj_property> |
| 39 | 43 |
</wvobject> |
| 40 |
- <wvobject fp_name="/e_testbed/system/core/regs/i_wr_data" type="array" db_ref_id="1"> |
|
| 41 |
- <obj_property name="ElementShortName">i_wr_data[31:0]</obj_property> |
|
| 42 |
- <obj_property name="ObjectShortName">i_wr_data[31:0]</obj_property> |
|
| 43 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 44 |
- </wvobject> |
|
| 45 |
- <wvobject fp_name="/e_testbed/system/core/alu/o_res" type="array" db_ref_id="1"> |
|
| 46 |
- <obj_property name="ElementShortName">o_res[31:0]</obj_property> |
|
| 47 |
- <obj_property name="ObjectShortName">o_res[31:0]</obj_property> |
|
| 48 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 49 |
- </wvobject> |
|
| 50 |
- <wvobject fp_name="/e_testbed/system/core/alu/i_op1" type="array" db_ref_id="1"> |
|
| 51 |
- <obj_property name="ElementShortName">i_op1[31:0]</obj_property> |
|
| 52 |
- <obj_property name="ObjectShortName">i_op1[31:0]</obj_property> |
|
| 53 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 54 |
- </wvobject> |
|
| 55 |
- <wvobject fp_name="/e_testbed/system/core/alu/i_op2" type="array" db_ref_id="1"> |
|
| 56 |
- <obj_property name="ElementShortName">i_op2[31:0]</obj_property> |
|
| 57 |
- <obj_property name="ObjectShortName">i_op2[31:0]</obj_property> |
|
| 58 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 59 |
- </wvobject> |
|
| 60 | 44 |
<wvobject fp_name="/e_testbed/system/core/o_instr_addr" type="array" db_ref_id="1"> |
| 61 | 45 |
<obj_property name="ElementShortName">o_instr_addr[31:0]</obj_property> |
| 62 | 46 |
<obj_property name="ObjectShortName">o_instr_addr[31:0]</obj_property> |
| ... | ... |
@@ -67,71 +51,36 @@ |
| 67 | 51 |
<obj_property name="ObjectShortName">i_instr_data[31:0]</obj_property> |
| 68 | 52 |
<obj_property name="Radix">HEXRADIX</obj_property> |
| 69 | 53 |
</wvobject> |
| 70 |
- <wvobject fp_name="/e_testbed/system/core/r_reg_s" type="array" db_ref_id="1"> |
|
| 71 |
- <obj_property name="ElementShortName">r_reg_s[4:0]</obj_property> |
|
| 72 |
- <obj_property name="ObjectShortName">r_reg_s[4:0]</obj_property> |
|
| 73 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 74 |
- </wvobject> |
|
| 75 |
- <wvobject fp_name="/e_testbed/system/core/r_reg_t" type="array" db_ref_id="1"> |
|
| 76 |
- <obj_property name="ElementShortName">r_reg_t[4:0]</obj_property> |
|
| 77 |
- <obj_property name="ObjectShortName">r_reg_t[4:0]</obj_property> |
|
| 78 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 79 |
- </wvobject> |
|
| 80 |
- <wvobject fp_name="/e_testbed/system/core/r_reg_d" type="array" db_ref_id="1"> |
|
| 81 |
- <obj_property name="ElementShortName">r_reg_d[4:0]</obj_property> |
|
| 82 |
- <obj_property name="ObjectShortName">r_reg_d[4:0]</obj_property> |
|
| 83 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 84 |
- </wvobject> |
|
| 85 |
- <wvobject fp_name="/e_testbed/system/core/r_imm_a" type="array" db_ref_id="1"> |
|
| 86 |
- <obj_property name="ElementShortName">r_imm_a[4:0]</obj_property> |
|
| 87 |
- <obj_property name="ObjectShortName">r_imm_a[4:0]</obj_property> |
|
| 88 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 89 |
- </wvobject> |
|
| 90 |
- <wvobject fp_name="/e_testbed/system/core/r_imm_16" type="array" db_ref_id="1"> |
|
| 91 |
- <obj_property name="ElementShortName">r_imm_16[15:0]</obj_property> |
|
| 92 |
- <obj_property name="ObjectShortName">r_imm_16[15:0]</obj_property> |
|
| 93 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 54 |
+ <wvobject fp_name="/e_testbed/system/core/s_stall" type="logic" db_ref_id="1"> |
|
| 55 |
+ <obj_property name="ElementShortName">s_stall</obj_property> |
|
| 56 |
+ <obj_property name="ObjectShortName">s_stall</obj_property> |
|
| 94 | 57 |
</wvobject> |
| 95 |
- <wvobject fp_name="/e_testbed/system/core/r_imm_26" type="array" db_ref_id="1"> |
|
| 96 |
- <obj_property name="ElementShortName">r_imm_26[25:0]</obj_property> |
|
| 97 |
- <obj_property name="ObjectShortName">r_imm_26[25:0]</obj_property> |
|
| 58 |
+ <wvobject fp_name="/e_testbed/system/uart/r_rx_data" type="array" db_ref_id="1"> |
|
| 59 |
+ <obj_property name="ElementShortName">r_rx_data[15:0]</obj_property> |
|
| 60 |
+ <obj_property name="ObjectShortName">r_rx_data[15:0]</obj_property> |
|
| 98 | 61 |
<obj_property name="Radix">HEXRADIX</obj_property> |
| 99 | 62 |
</wvobject> |
| 100 |
- <wvobject fp_name="/e_testbed/system/core/r_op" type="other" db_ref_id="1"> |
|
| 101 |
- <obj_property name="ElementShortName">r_op</obj_property> |
|
| 102 |
- <obj_property name="ObjectShortName">r_op</obj_property> |
|
| 103 |
- </wvobject> |
|
| 104 |
- <wvobject fp_name="/e_testbed/system/core/r_link" type="other" db_ref_id="1"> |
|
| 105 |
- <obj_property name="ElementShortName">r_link</obj_property> |
|
| 106 |
- <obj_property name="ObjectShortName">r_link</obj_property> |
|
| 63 |
+ <wvobject fp_name="/e_testbed/system/uart/r_rx_samples" type="array" db_ref_id="1"> |
|
| 64 |
+ <obj_property name="ElementShortName">r_rx_samples[1:0]</obj_property> |
|
| 65 |
+ <obj_property name="ObjectShortName">r_rx_samples[1:0]</obj_property> |
|
| 66 |
+ <obj_property name="Radix">BINARYRADIX</obj_property> |
|
| 107 | 67 |
</wvobject> |
| 108 |
- <wvobject fp_name="/e_testbed/system/core/r_cmp" type="other" db_ref_id="1"> |
|
| 109 |
- <obj_property name="ElementShortName">r_cmp</obj_property> |
|
| 110 |
- <obj_property name="ObjectShortName">r_cmp</obj_property> |
|
| 68 |
+ <wvobject fp_name="/e_testbed/system/uart/r_rx_bit" type="other" db_ref_id="1"> |
|
| 69 |
+ <obj_property name="ElementShortName">r_rx_bit</obj_property> |
|
| 70 |
+ <obj_property name="ObjectShortName">r_rx_bit</obj_property> |
|
| 111 | 71 |
</wvobject> |
| 112 |
- <wvobject fp_name="/e_testbed/system/core/r_alu" type="other" db_ref_id="1"> |
|
| 113 |
- <obj_property name="ElementShortName">r_alu</obj_property> |
|
| 114 |
- <obj_property name="ObjectShortName">r_alu</obj_property> |
|
| 72 |
+ <wvobject fp_name="/e_testbed/system/uart/r_rx_sample" type="other" db_ref_id="1"> |
|
| 73 |
+ <obj_property name="DisplayName">label</obj_property> |
|
| 74 |
+ <obj_property name="ElementShortName">r_rx_sample</obj_property> |
|
| 75 |
+ <obj_property name="ObjectShortName">r_rx_sample</obj_property> |
|
| 76 |
+ <obj_property name="label">r_rx_sample</obj_property> |
|
| 115 | 77 |
</wvobject> |
| 116 |
- <wvobject fp_name="/e_testbed/system/core/r_imm" type="other" db_ref_id="1"> |
|
| 117 |
- <obj_property name="ElementShortName">r_imm</obj_property> |
|
| 118 |
- <obj_property name="ObjectShortName">r_imm</obj_property> |
|
| 119 |
- </wvobject> |
|
| 120 |
- <wvobject fp_name="/e_testbed/system/core/r_ldst" type="other" db_ref_id="1"> |
|
| 121 |
- <obj_property name="ElementShortName">r_ldst</obj_property> |
|
| 122 |
- <obj_property name="ObjectShortName">r_ldst</obj_property> |
|
| 123 |
- </wvobject> |
|
| 124 |
- <wvobject fp_name="/e_testbed/system/core/regs/r_regs[2]" type="array" db_ref_id="1"> |
|
| 125 |
- <obj_property name="ElementShortName">[2]</obj_property> |
|
| 126 |
- <obj_property name="ObjectShortName">r_regs[2]</obj_property> |
|
| 127 |
- <obj_property name="Radix">HEXRADIX</obj_property> |
|
| 128 |
- </wvobject> |
|
| 129 |
- <wvobject fp_name="/e_testbed/system/core/s_stall" type="logic" db_ref_id="1"> |
|
| 130 |
- <obj_property name="ElementShortName">s_stall</obj_property> |
|
| 131 |
- <obj_property name="ObjectShortName">s_stall</obj_property> |
|
| 78 |
+ <wvobject fp_name="/e_testbed/system/uart/r_rx_cnt" type="other" db_ref_id="1"> |
|
| 79 |
+ <obj_property name="ElementShortName">r_rx_cnt</obj_property> |
|
| 80 |
+ <obj_property name="ObjectShortName">r_rx_cnt</obj_property> |
|
| 132 | 81 |
</wvobject> |
| 133 |
- <wvobject fp_name="/e_testbed/system/core/regs/i_wr_en" type="logic" db_ref_id="1"> |
|
| 134 |
- <obj_property name="ElementShortName">i_wr_en</obj_property> |
|
| 135 |
- <obj_property name="ObjectShortName">i_wr_en</obj_property> |
|
| 82 |
+ <wvobject fp_name="/e_testbed/system/uart/r_rx_state" type="other" db_ref_id="1"> |
|
| 83 |
+ <obj_property name="ElementShortName">r_rx_state</obj_property> |
|
| 84 |
+ <obj_property name="ObjectShortName">r_rx_state</obj_property> |
|
| 136 | 85 |
</wvobject> |
| 137 | 86 |
</wave_config> |
| ... | ... |
@@ -4,6 +4,10 @@ |
| 4 | 4 |
#include "uart.h" |
| 5 | 5 |
#include "switches.h" |
| 6 | 6 |
|
| 7 |
+//#define CFG_DELAY |
|
| 8 |
+//#define CFG_LCD |
|
| 9 |
+#define CFG_UART |
|
| 10 |
+ |
|
| 7 | 11 |
const int myconst = 0x12345678; |
| 8 | 12 |
|
| 9 | 13 |
int myvar = 0x11223344; |
| ... | ... |
@@ -12,6 +16,7 @@ volatile int data[100]; |
| 12 | 16 |
|
| 13 | 17 |
void switches(void) |
| 14 | 18 |
{
|
| 19 |
+#ifdef CFG_LCD |
|
| 15 | 20 |
lcd_chr(1, 0, switches_get_state(sw_0) ? '0' : ' '); |
| 16 | 21 |
lcd_chr(1, 1, switches_get_state(sw_1) ? '1' : ' '); |
| 17 | 22 |
lcd_chr(1, 2, switches_get_state(sw_2) ? '2' : ' '); |
| ... | ... |
@@ -23,12 +28,15 @@ void switches(void) |
| 23 | 28 |
lcd_chr(1, 8, switches_get_state(sw_center) ? 'C' : ' '); |
| 24 | 29 |
lcd_chr(1, 9, switches_get_state(sw_rot_a) ? 'a' : ' '); |
| 25 | 30 |
lcd_chr(1, 10, switches_get_state(sw_rot_b) ? 'b' : ' '); |
| 31 |
+#endif |
|
| 26 | 32 |
|
| 33 |
+#ifdef CFG_LCD |
|
| 27 | 34 |
unsigned int cnt = switches_get_rot_cnt(); |
| 28 | 35 |
lcd_chr(1, 12, '0' + (cnt >> 9 & 0x7)); |
| 29 | 36 |
lcd_chr(1, 13, '0' + (cnt >> 6 & 0x7)); |
| 30 | 37 |
lcd_chr(1, 14, '0' + (cnt >> 3 & 0x7)); |
| 31 | 38 |
lcd_chr(1, 15, '0' + (cnt & 0x7)); |
| 39 |
+#endif |
|
| 32 | 40 |
} |
| 33 | 41 |
|
| 34 | 42 |
void delay(void) |
| ... | ... |
@@ -36,7 +44,9 @@ void delay(void) |
| 36 | 44 |
unsigned int i; |
| 37 | 45 |
for (i = 0; i < 10; ++i) {
|
| 38 | 46 |
switches(); |
| 47 |
+#ifdef CFG_DELAY |
|
| 39 | 48 |
cyc_cnt_delay_ms(20); |
| 49 |
+#endif |
|
| 40 | 50 |
} |
| 41 | 51 |
} |
| 42 | 52 |
|
| ... | ... |
@@ -47,10 +57,13 @@ int main() |
| 47 | 57 |
for (i = 0; i < sizeof(data) / sizeof(data[0]); ++i) |
| 48 | 58 |
data[i] = i; |
| 49 | 59 |
|
| 60 |
+#ifdef CFG_LCD |
|
| 50 | 61 |
lcd_init(); |
| 51 | 62 |
lcd_str(0, "MIPS I system"); |
| 52 | 63 |
lcd_str(1, ""); |
| 64 |
+#endif |
|
| 53 | 65 |
|
| 66 |
+#ifdef CFG_UART |
|
| 54 | 67 |
uart_cfg_scale(62); /* 115200 */ |
| 55 | 68 |
uart_cfg_bits(8); |
| 56 | 69 |
uart_cfg_stop(1); |
| ... | ... |
@@ -62,6 +75,7 @@ int main() |
| 62 | 75 |
uart_tx('I');
|
| 63 | 76 |
uart_tx('\r');
|
| 64 | 77 |
uart_tx('\n');
|
| 78 |
+#endif |
|
| 65 | 79 |
|
| 66 | 80 |
while (1) {
|
| 67 | 81 |
for (i = 0x1; i < 0x80; i <<= 1) {
|
| ... | ... |
@@ -10,6 +10,7 @@ ENTITY e_io_uart IS |
| 10 | 10 |
o_rd_data: OUT std_logic_vector(31 DOWNTO 0); |
| 11 | 11 |
i_wr_data: IN std_logic_vector(31 DOWNTO 0); |
| 12 | 12 |
i_wr_en: IN std_logic_vector( 3 DOWNTO 0); |
| 13 |
+ pin_i_rx: IN std_logic; |
|
| 13 | 14 |
pin_o_tx: OUT std_logic |
| 14 | 15 |
); |
| 15 | 16 |
END ENTITY e_io_uart; |
| ... | ... |
@@ -25,6 +26,25 @@ ARCHITECTURE a_io_uart OF e_io_uart IS |
| 25 | 26 |
SIGNAL n_cfg_stop: std_logic_vector( 1 DOWNTO 0); |
| 26 | 27 |
SIGNAL r_cfg_stop: std_logic_vector( 1 DOWNTO 0) := "01"; |
| 27 | 28 |
|
| 29 |
+ SIGNAL n_rx_scale: natural RANGE 2**16 - 1 DOWNTO 0; |
|
| 30 |
+ SIGNAL r_rx_scale: natural RANGE 2**16 - 1 DOWNTO 0 := 1; |
|
| 31 |
+ SIGNAL n_rx_bits: natural RANGE 15 DOWNTO 0; |
|
| 32 |
+ SIGNAL r_rx_bits: natural RANGE 15 DOWNTO 0 := 1; |
|
| 33 |
+ SIGNAL n_rx_stop: natural RANGE 3 DOWNTO 0; |
|
| 34 |
+ SIGNAL r_rx_stop: natural RANGE 3 DOWNTO 0 := 1; |
|
| 35 |
+ SIGNAL n_rx_state: t_state; |
|
| 36 |
+ SIGNAL r_rx_state: t_state := inactive; |
|
| 37 |
+ SIGNAL n_rx_cnt: natural RANGE 2**16 - 1 DOWNTO 0; |
|
| 38 |
+ SIGNAL r_rx_cnt: natural RANGE 2**16 - 1 DOWNTO 0 := 0; |
|
| 39 |
+ SIGNAL n_rx_sample: natural RANGE 6 DOWNTO 0; |
|
| 40 |
+ SIGNAL r_rx_sample: natural RANGE 6 DOWNTO 0 := 0; |
|
| 41 |
+ SIGNAL n_rx_bit: natural RANGE 15 DOWNTO 0; |
|
| 42 |
+ SIGNAL r_rx_bit: natural RANGE 15 DOWNTO 0 := 0; |
|
| 43 |
+ SIGNAL n_rx_samples: std_logic_vector( 1 DOWNTO 0); |
|
| 44 |
+ SIGNAL r_rx_samples: std_logic_vector( 1 DOWNTO 0) := "00"; |
|
| 45 |
+ SIGNAL n_rx_data: std_logic_vector(15 DOWNTO 0); |
|
| 46 |
+ SIGNAL r_rx_data: std_logic_vector(15 DOWNTO 0) := X"0000"; |
|
| 47 |
+ |
|
| 28 | 48 |
SIGNAL n_tx_scale: natural RANGE 2**16 - 1 DOWNTO 0; |
| 29 | 49 |
SIGNAL r_tx_scale: natural RANGE 2**16 - 1 DOWNTO 0 := 1; |
| 30 | 50 |
SIGNAL n_tx_bits: natural RANGE 15 DOWNTO 0; |
| ... | ... |
@@ -81,6 +101,141 @@ BEGIN |
| 81 | 101 |
END IF; |
| 82 | 102 |
END PROCESS p_cfg_sync; |
| 83 | 103 |
|
| 104 |
+ p_rx_next: PROCESS(r_cfg_scale, r_cfg_bits, r_cfg_stop, |
|
| 105 |
+ r_rx_scale, r_rx_bits, r_rx_stop, |
|
| 106 |
+ r_rx_state, r_rx_cnt, r_rx_sample, r_rx_bit, |
|
| 107 |
+ r_rx_samples, r_rx_data, |
|
| 108 |
+ pin_i_rx) |
|
| 109 |
+ VARIABLE v_next_cnt: boolean; |
|
| 110 |
+ VARIABLE v_next_sample: boolean; |
|
| 111 |
+ VARIABLE v_next_bit: boolean; |
|
| 112 |
+ VARIABLE v_next_state: boolean; |
|
| 113 |
+ VARIABLE v_bits: natural RANGE 15 DOWNTO 0; |
|
| 114 |
+ VARIABLE v_samples: std_logic_vector(2 DOWNTO 0); |
|
| 115 |
+ VARIABLE v_bit_val: std_logic; |
|
| 116 |
+ VARIABLE v_err: boolean; |
|
| 117 |
+ BEGIN |
|
| 118 |
+ n_rx_scale <= r_rx_scale; |
|
| 119 |
+ n_rx_bits <= r_rx_bits; |
|
| 120 |
+ n_rx_stop <= r_rx_stop; |
|
| 121 |
+ n_rx_state <= r_rx_state; |
|
| 122 |
+ n_rx_cnt <= r_rx_cnt; |
|
| 123 |
+ n_rx_sample <= r_rx_sample; |
|
| 124 |
+ n_rx_bit <= r_rx_bit; |
|
| 125 |
+ n_rx_samples <= r_rx_samples; |
|
| 126 |
+ n_rx_data <= r_rx_data; |
|
| 127 |
+ v_next_cnt := false; |
|
| 128 |
+ v_next_sample := false; |
|
| 129 |
+ v_next_bit := false; |
|
| 130 |
+ v_next_state := false; |
|
| 131 |
+ v_bits := 0; |
|
| 132 |
+ v_samples := "000"; |
|
| 133 |
+ v_bit_val := '0'; |
|
| 134 |
+ v_err := false; |
|
| 135 |
+ IF r_rx_state = inactive THEN |
|
| 136 |
+ IF pin_i_rx = '0' THEN |
|
| 137 |
+ n_rx_scale <= to_integer(unsigned(r_cfg_scale)); |
|
| 138 |
+ n_rx_bits <= to_integer(unsigned(r_cfg_bits)); |
|
| 139 |
+ n_rx_stop <= to_integer(unsigned(r_cfg_stop)); |
|
| 140 |
+ n_rx_state <= start; |
|
| 141 |
+ n_rx_cnt <= 0; |
|
| 142 |
+ n_rx_sample <= 3; -- sample in middle of received bits |
|
| 143 |
+ n_rx_bit <= 0; |
|
| 144 |
+ n_rx_samples <= "00"; |
|
| 145 |
+ n_rx_data <= X"0000"; |
|
| 146 |
+ END IF; |
|
| 147 |
+ ELSE |
|
| 148 |
+ v_next_cnt := true; |
|
| 149 |
+ END IF; |
|
| 150 |
+ IF v_next_cnt THEN |
|
| 151 |
+ IF r_rx_cnt + 1 /= r_rx_scale THEN |
|
| 152 |
+ n_rx_cnt <= r_rx_cnt + 1; |
|
| 153 |
+ ELSE |
|
| 154 |
+ n_rx_cnt <= 0; |
|
| 155 |
+ v_next_sample := true; |
|
| 156 |
+ END IF; |
|
| 157 |
+ END IF; |
|
| 158 |
+ IF v_next_sample THEN |
|
| 159 |
+ IF r_rx_sample = 4 THEN |
|
| 160 |
+ n_rx_samples(0) <= pin_i_rx; |
|
| 161 |
+ ELSIF r_rx_sample = 5 THEN |
|
| 162 |
+ n_rx_samples(1) <= pin_i_rx; |
|
| 163 |
+ ELSIF r_rx_sample = 6 THEN |
|
| 164 |
+ v_samples := pin_i_rx & r_rx_samples; |
|
| 165 |
+ CASE v_samples IS |
|
| 166 |
+ WHEN "000" | "001" | "010" | "100" => v_bit_val := '0'; |
|
| 167 |
+ WHEN "011" | "101" | "110" | "111" => v_bit_val := '1'; |
|
| 168 |
+ WHEN OTHERS => NULL; |
|
| 169 |
+ END CASE; |
|
| 170 |
+ IF r_rx_state = data THEN |
|
| 171 |
+ n_rx_data(r_rx_bit) <= v_bit_val; |
|
| 172 |
+ END IF; |
|
| 173 |
+ CASE r_rx_state IS |
|
| 174 |
+ WHEN start => v_err := v_bit_val /= '0'; |
|
| 175 |
+ WHEN data => v_err := false; |
|
| 176 |
+ WHEN stop => v_err := v_bit_val /= '1'; |
|
| 177 |
+ WHEN OTHERS => NULL; |
|
| 178 |
+ END CASE; |
|
| 179 |
+ IF v_err THEN |
|
| 180 |
+ n_rx_data(15) <= '1'; |
|
| 181 |
+ END IF; |
|
| 182 |
+ END IF; |
|
| 183 |
+ IF r_rx_sample /= 6 THEN |
|
| 184 |
+ n_rx_sample <= r_rx_sample + 1; |
|
| 185 |
+ ELSE |
|
| 186 |
+ n_rx_sample <= 0; |
|
| 187 |
+ v_next_bit := true; |
|
| 188 |
+ END IF; |
|
| 189 |
+ END IF; |
|
| 190 |
+ IF v_next_bit THEN |
|
| 191 |
+ CASE r_rx_state IS |
|
| 192 |
+ WHEN start => v_bits := 1; |
|
| 193 |
+ WHEN data => v_bits := r_rx_bits; |
|
| 194 |
+ WHEN stop => v_bits := r_rx_stop; |
|
| 195 |
+ WHEN OTHERS => NULL; |
|
| 196 |
+ END CASE; |
|
| 197 |
+ IF r_rx_bit + 1 /= v_bits THEN |
|
| 198 |
+ n_rx_bit <= r_rx_bit + 1; |
|
| 199 |
+ ELSE |
|
| 200 |
+ n_rx_bit <= 0; |
|
| 201 |
+ v_next_state := true; |
|
| 202 |
+ END IF; |
|
| 203 |
+ END IF; |
|
| 204 |
+ IF v_next_state THEN |
|
| 205 |
+ CASE r_rx_state IS |
|
| 206 |
+ WHEN start => n_rx_state <= data; |
|
| 207 |
+ WHEN data => n_rx_state <= stop; |
|
| 208 |
+ WHEN stop => n_rx_state <= inactive; |
|
| 209 |
+ WHEN OTHERS => NULL; |
|
| 210 |
+ END CASE; |
|
| 211 |
+ END IF; |
|
| 212 |
+ END PROCESS p_rx_next; |
|
| 213 |
+ |
|
| 214 |
+ p_rx_sync: PROCESS(rst, clk) |
|
| 215 |
+ BEGIN |
|
| 216 |
+ IF rst = '1' THEN |
|
| 217 |
+ r_rx_scale <= 1; |
|
| 218 |
+ r_rx_bits <= 1; |
|
| 219 |
+ r_rx_stop <= 1; |
|
| 220 |
+ r_rx_state <= inactive; |
|
| 221 |
+ r_rx_cnt <= 0; |
|
| 222 |
+ r_rx_sample <= 0; |
|
| 223 |
+ r_rx_bit <= 0; |
|
| 224 |
+ r_rx_samples <= "00"; |
|
| 225 |
+ r_rx_data <= X"0000"; |
|
| 226 |
+ ELSIF rising_edge(clk) THEN |
|
| 227 |
+ r_rx_scale <= n_rx_scale; |
|
| 228 |
+ r_rx_bits <= n_rx_bits; |
|
| 229 |
+ r_rx_stop <= n_rx_stop; |
|
| 230 |
+ r_rx_state <= n_rx_state; |
|
| 231 |
+ r_rx_cnt <= n_rx_cnt; |
|
| 232 |
+ r_rx_sample <= n_rx_sample; |
|
| 233 |
+ r_rx_bit <= n_rx_bit; |
|
| 234 |
+ r_rx_samples <= n_rx_samples; |
|
| 235 |
+ r_rx_data <= n_rx_data; |
|
| 236 |
+ END IF; |
|
| 237 |
+ END PROCESS p_rx_sync; |
|
| 238 |
+ |
|
| 84 | 239 |
p_tx_next: PROCESS(r_cfg_scale, r_cfg_bits, r_cfg_stop, |
| 85 | 240 |
r_tx_scale, r_tx_bits, r_tx_stop, |
| 86 | 241 |
r_tx_state, r_tx_cnt, r_tx_sample, r_tx_bit, r_tx_data, |
| ... | ... |
@@ -127,7 +282,7 @@ BEGIN |
| 127 | 282 |
END IF; |
| 128 | 283 |
END IF; |
| 129 | 284 |
IF v_next_sample THEN |
| 130 |
- IF r_tx_sample + 1 /= 7 THEN |
|
| 285 |
+ IF r_tx_sample /= 6 THEN |
|
| 131 | 286 |
n_tx_sample <= r_tx_sample + 1; |
| 132 | 287 |
ELSE |
| 133 | 288 |
n_tx_sample <= 0; |
| ... | ... |
@@ -10,6 +10,7 @@ ENTITY e_system IS |
| 10 | 10 |
pin_o_leds: OUT std_logic_vector(7 DOWNTO 0); |
| 11 | 11 |
pin_o_lcd: OUT t_io_lcd_pins; |
| 12 | 12 |
pin_i_switches: IN t_io_switches_pins; |
| 13 |
+ pin_i_uart_rx: IN std_logic; |
|
| 13 | 14 |
pin_o_uart_tx: OUT std_logic |
| 14 | 15 |
); |
| 15 | 16 |
END ENTITY e_system; |
| ... | ... |
@@ -161,6 +162,7 @@ ARCHITECTURE a_system OF e_system IS |
| 161 | 162 |
o_rd_data: OUT std_logic_vector(31 DOWNTO 0); |
| 162 | 163 |
i_wr_data: IN std_logic_vector(31 DOWNTO 0); |
| 163 | 164 |
i_wr_en: IN std_logic_vector( 3 DOWNTO 0); |
| 165 |
+ pin_i_rx: IN std_logic; |
|
| 164 | 166 |
pin_o_tx: OUT std_logic |
| 165 | 167 |
); |
| 166 | 168 |
END COMPONENT e_io_uart; |
| ... | ... |
@@ -342,6 +344,7 @@ BEGIN |
| 342 | 344 |
o_rd_data => s_uart_rd_data, |
| 343 | 345 |
i_wr_data => s_uart_wr_data, |
| 344 | 346 |
i_wr_en => s_uart_wr_en, |
| 347 |
+ pin_i_rx => pin_i_uart_rx, |
|
| 345 | 348 |
pin_o_tx => pin_o_uart_tx |
| 346 | 349 |
); |
| 347 | 350 |
|
| ... | ... |
@@ -16,6 +16,7 @@ ARCHITECTURE a_testbed OF e_testbed IS |
| 16 | 16 |
pin_o_leds: OUT std_logic_vector(7 DOWNTO 0); |
| 17 | 17 |
pin_o_lcd: OUT t_io_lcd_pins; |
| 18 | 18 |
pin_i_switches: IN t_io_switches_pins; |
| 19 |
+ pin_i_uart_rx: IN std_logic; |
|
| 19 | 20 |
pin_o_uart_tx: OUT std_logic |
| 20 | 21 |
); |
| 21 | 22 |
END COMPONENT e_system; |
| ... | ... |
@@ -23,7 +24,7 @@ ARCHITECTURE a_testbed OF e_testbed IS |
| 23 | 24 |
SIGNAL s_clk: std_logic; |
| 24 | 25 |
SIGNAL pin_leds: std_logic_vector(7 DOWNTO 0); |
| 25 | 26 |
SIGNAL pin_lcd: t_io_lcd_pins; |
| 26 |
- SIGNAL pin_uart_tx: std_logic; |
|
| 27 |
+ SIGNAL pin_uart_loopback: std_logic; |
|
| 27 | 28 |
|
| 28 | 29 |
BEGIN |
| 29 | 30 |
|
| ... | ... |
@@ -33,7 +34,8 @@ BEGIN |
| 33 | 34 |
pin_o_leds => pin_leds, |
| 34 | 35 |
pin_o_lcd => pin_lcd, |
| 35 | 36 |
pin_i_switches => (sw => (OTHERS => '0'), OTHERS => '0'), |
| 36 |
- pin_o_uart_tx => pin_uart_tx |
|
| 37 |
+ pin_i_uart_rx => pin_uart_loopback, |
|
| 38 |
+ pin_o_uart_tx => pin_uart_loopback |
|
| 37 | 39 |
); |
| 38 | 40 |
|
| 39 | 41 |
p_rst_clk: PROCESS |
| 40 | 42 |