mips_sys

@@ -7,6 +7,7 @@

 //#define CFG_DELAY

 //#define CFG_LCD

 #define CFG_UART

+#define CFG_UART_CHK

 const int myconst = 0x12345678;

@@ -75,6 +76,16 @@ int main()

   uart_tx('I');

   uart_tx('\r');

   uart_tx('\n');

+#ifdef CFG_UART_CHK

+  if (uart_rx() != 'M') while(1);

+  if (uart_rx() != 'I') while(1);

+  if (uart_rx() != 'P') while(1);

+  if (uart_rx() != 'S') while(1);

+  if (uart_rx() != ' ') while(1);

+  if (uart_rx() != 'I') while(1);

+  if (uart_rx() != '\r') while(1);

+  if (uart_rx() != '\n') while(1);

+#endif

 #endif

   while (1) {

@@ -36,7 +36,19 @@ void uart_cfg_stop(unsigned char stop)

  */

 void uart_tx(unsigned short chr)

 {

-  while (!*(uart_ptr + 4));

-  *(unsigned short *)(uart_ptr + 8) = chr;

+  while (!*(uart_ptr + 4)); /* wait for ready */

+  *(unsigned short *)(uart_ptr + 8) = chr; /* write data */

+}

+

+/**

+ * @brief receive a character

+ * @return character received

+ */

+unsigned short uart_rx(void)

+{

+  while (!*(uart_ptr + 5)); /* wait for data */

+  unsigned short chr = *(unsigned short *)(uart_ptr + 12); /* read data */

+  *(unsigned short *)(uart_ptr + 12) = 0; /* remove data from FIFO */

+  return chr;

 }

@@ -25,6 +25,11 @@ void uart_cfg_stop(unsigned char stop);

  */

 void uart_tx(unsigned short chr);

+/**

+ * @brief receive a character

+ * @return character received

+ */

+unsigned short uart_rx(void);

 #endif /* #ifndef UART_H */

@@ -26,6 +26,13 @@ ARCHITECTURE a_io_uart OF e_io_uart IS

     SIGNAL n_cfg_stop:  std_logic_vector( 1 DOWNTO 0);

     SIGNAL r_cfg_stop:  std_logic_vector( 1 DOWNTO 0) := "01";

+    SIGNAL s_rx_wr_rdy:  std_logic;

+    SIGNAL s_rx_wr_data: std_logic_vector(15 DOWNTO 0);

+    SIGNAL s_rx_wr_en:   std_logic;

+    SIGNAL s_rx_rd_rdy:  std_logic;

+    SIGNAL s_rx_rd_data: std_logic_vector(15 DOWNTO 0);

+    SIGNAL s_rx_rd_en:   std_logic;

+

     SIGNAL n_rx_scale:   natural RANGE 2**16 - 1 DOWNTO 0;

     SIGNAL r_rx_scale:   natural RANGE 2**16 - 1 DOWNTO 0 := 1;

     SIGNAL n_rx_bits:    natural RANGE 15        DOWNTO 0;

@@ -124,20 +131,42 @@ BEGIN

         END IF;

     END PROCESS p_cfg_sync;

+    s_rx_rd_en <= '1' WHEN i_addr = "11" AND i_wr_en(1 DOWNTO 0) = "11"

+                  ELSE '0';

+

+    rx_fifo: e_block_fifo

+        GENERIC MAP (

+            addr_width => 4,

+            data_width => 16

+        )

+        PORT MAP (

+            rst       => rst,

+            clk       => clk,

+            o_wr_rdy  => s_rx_wr_rdy,

+            i_wr_data => s_rx_wr_data,

+            i_wr_en   => s_rx_wr_en,

+            o_rd_rdy  => s_rx_rd_rdy,

+            o_rd_data => s_rx_rd_data,

+            i_rd_en   => s_rx_rd_en

+        );

+

     p_rx_next: PROCESS(r_cfg_scale, r_cfg_bits, r_cfg_stop,

                        r_rx_scale, r_rx_bits, r_rx_stop,

                        r_rx_state, r_rx_cnt, r_rx_sample, r_rx_bit,

                        r_rx_samples, r_rx_data,

-                       pin_i_rx)

+                       pin_i_rx, s_rx_wr_rdy)

         VARIABLE v_next_cnt:    boolean;

         VARIABLE v_next_sample: boolean;

         VARIABLE v_next_bit:    boolean;

         VARIABLE v_next_state:  boolean;

+        VARIABLE v_complete:    boolean;

         VARIABLE v_bits:        natural RANGE 15 DOWNTO 0;

         VARIABLE v_samples:     std_logic_vector( 2 DOWNTO 0);

         VARIABLE v_bit_val:     std_logic;

-        VARIABLE v_err:         boolean;

+        VARIABLE v_data:        std_logic_vector(15 DOWNTO 0);

     BEGIN

+        s_rx_wr_data <= (OTHERS => '0');

+        s_rx_wr_en   <= '0';

         n_rx_scale   <= r_rx_scale;

         n_rx_bits    <= r_rx_bits;

         n_rx_stop    <= r_rx_stop;

@@ -146,15 +175,15 @@ BEGIN

         n_rx_sample  <= r_rx_sample;

         n_rx_bit     <= r_rx_bit;

         n_rx_samples <= r_rx_samples;

-        n_rx_data    <= r_rx_data;

         v_next_cnt    := false;

         v_next_sample := false;

         v_next_bit    := false;

         v_next_state  := false;

+        v_complete    := false;

         v_bits        := 0;

         v_samples     := "000";

         v_bit_val     := '0';

-        v_err         := false;

+        v_data        := r_rx_data;

         IF r_rx_state = inactive THEN

             IF pin_i_rx = '0' THEN

                 n_rx_scale   <= to_integer(unsigned(r_cfg_scale));

@@ -164,8 +193,8 @@ BEGIN

                 n_rx_cnt     <= 0;

                 n_rx_sample  <= 3; -- sample in middle of received bits

                 n_rx_bit     <= 0;

-                n_rx_samples <= "00";

-                n_rx_data    <= X"0000";

+                -- n_rx_samples: no initialization needed

+                -- n_rx_data/v_data: keep error bit (bit 15), no initialization needed for other bits

             END IF;

         ELSE

             v_next_cnt := true;

@@ -190,18 +219,19 @@ BEGIN

                    WHEN "011" | "101" | "110" | "111" => v_bit_val := '1';

                    WHEN OTHERS => NULL;

                 END CASE;

-                IF r_rx_state = data THEN

-                    n_rx_data(r_rx_bit) <= v_bit_val;

-                END IF;

                 CASE r_rx_state IS

-                    WHEN start => v_err := v_bit_val /= '0';

-                    WHEN data  => v_err := false;

-                    WHEN stop  => v_err := v_bit_val /= '1';

+                    WHEN start =>

+                        IF v_bit_val /= '0' THEN

+                            v_data(15) := '1'; -- set error bit

+                        END IF;

+                    WHEN data  =>

+                        v_data(r_rx_bit) := v_bit_val;

+                    WHEN stop  =>

+                        IF v_bit_val /= '1' THEN

+                            v_data(15) := '1'; -- set error bit

+                        END IF;

                     WHEN OTHERS => NULL;

                 END CASE;

-                IF v_err THEN

-                    n_rx_data(15) <= '1';

-                END IF;

             END IF;

             IF r_rx_sample /= 6 THEN

                 n_rx_sample <= r_rx_sample + 1;

@@ -228,10 +258,20 @@ BEGIN

             CASE r_rx_state IS

                 WHEN start => n_rx_state <= data;

                 WHEN data  => n_rx_state <= stop;

-                WHEN stop  => n_rx_state <= inactive;

+                WHEN stop  => n_rx_state <= inactive; v_complete := true;

                 WHEN OTHERS => NULL;

             END CASE;

         END IF;

+        IF v_complete THEN

+            IF s_rx_wr_rdy = '1' THEN

+                s_rx_wr_data <= v_data;

+                s_rx_wr_en   <= '1';

+                v_data(15)   := '0'; -- clear error bit

+            ELSE

+                v_data(15)   := '1'; -- set error bit (RX FIFO overflow)

+            END IF;

+        END IF;

+        n_rx_data <= v_data;

     END PROCESS p_rx_next;

     p_rx_sync: PROCESS(rst, clk)

@@ -404,6 +444,9 @@ BEGIN

                     o_rd_data(25 DOWNTO 24) <= r_cfg_stop;

                 WHEN "01" =>

                     o_rd_data(0) <= s_tx_wr_rdy;

+                    o_rd_data(8) <= s_rx_rd_rdy;

+                WHEN "11" =>

+                    o_rd_data(15 DOWNTO 0) <= s_rx_rd_data;

                 WHEN OTHERS =>

                     NULL;

             END CASE;