MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
read peripherals with one cycle delay - as for memory
fe7741d @ 2012-02-12 19:10:11
| constraints | implemented LCD peripheral | 2012-02-12 15:31:45 |
|---|---|---|
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | converted code to use constants in data memory | 2012-02-12 18:24:53 |
| io | read peripherals with one cycle delay - as for memory | 2012-02-12 19:10:11 |
| mips | add initial values for registers | 2012-02-12 18:05:38 |
| system | implemented loading of data memory from firmware | 2012-02-12 17:47:50 |
| test | implemented LCD peripheral | 2012-02-12 15:31:45 |
| .gitignore | impact project | 2012-02-11 00:32:06 |
| Default.wcfg | implemented LCD peripheral | 2012-02-12 15:31:45 |
| mips_sys.ipf | impact project | 2012-02-11 00:32:06 |
| mips_sys.xise | implemented loading of data memory from firmware | 2012-02-12 17:47:50 |