read peripherals with one cycle delay - as for memory (fe7741d) - mips_sys · BlinkenArea

read peripherals with one cycle delay - as for memory

Stefan Schuermans commited on 2012-02-12 19:10:11
Showing 3 changed files, with 41 additions and 20 deletions.

io/cyc_cnt.vhd 7e610ca..17676a3
io/lcd.vhd 47a5125..ff19a08
io/leds.vhd a25126c..0ca6399

io/cyc_cnt.vhd

@@ -19,8 +19,6 @@ ARCHITECTURE a_io_cyc_cnt OF e_io_cyc_cnt IS
 
 BEGIN
 
-    o_rd_data <= r_cnt;
-
     p_write: PROCESS(r_cnt, i_wr_data, i_wr_en)
     BEGIN
         IF i_wr_en = '1' THEN
@@ -39,5 +37,14 @@ BEGIN
         END IF;
     END PROCESS p_sync;
 
+    p_read: PROCESS(rst, clk)
+    BEGIN
+        IF rst = '1' THEN
+            o_rd_data <= (OTHERS => '0');
+        ELSIF rising_edge(clk) THEN
+            o_rd_data <= r_cnt;
+        END IF;
+    END PROCESS p_read;
+
 END ARCHITECTURE a_io_cyc_cnt;
 

io/lcd.vhd

View file @ fe7741d

@@ -22,15 +22,7 @@ ARCHITECTURE a_io_lcd OF e_io_lcd IS
 
 BEGIN
 
-    o_rd_data( 7 DOWNTO  0) <= r_lcd.data;
-    o_rd_data( 8)           <= r_lcd.e;
-    o_rd_data(15 DOWNTO  9) <= (OTHERS => '0');
-    o_rd_data(16)           <= r_lcd.rs;
-    o_rd_data(23 DOWNTO 17) <= (OTHERS => '0');
-    o_rd_data(24)           <= r_lcd.rw;
-    o_rd_data(31 DOWNTO 25) <= (OTHERS => '0');
-
-    p_write: PROCESS(r_lcd, i_wr_data, i_wr_en)
+    p_next: PROCESS(r_lcd, i_wr_data, i_wr_en)
     BEGIN
         IF i_wr_en(0) = '1' THEN
             n_lcd.data <= i_wr_data(7 DOWNTO 0);
@@ -52,9 +44,7 @@ BEGIN
         ELSE
             n_lcd.rw <= r_lcd.rw;
         END IF;
-    END PROCESS p_write;
-
-    pin_o_lcd <= r_lcd;
+    END PROCESS p_next;
 
     p_sync: PROCESS(rst, clk)
     BEGIN
@@ -68,5 +58,22 @@ BEGIN
         END IF;
     END PROCESS p_sync;
 
+    p_read: PROCESS(rst, clk)
+    BEGIN
+        IF rst = '1' THEN
+            o_rd_data <= (OTHERS => '0');
+        ELSIF rising_edge(clk) THEN
+            o_rd_data( 7 DOWNTO  0) <= r_lcd.data;
+            o_rd_data( 8)           <= r_lcd.e;
+            o_rd_data(15 DOWNTO  9) <= (OTHERS => '0');
+            o_rd_data(16)           <= r_lcd.rs;
+            o_rd_data(23 DOWNTO 17) <= (OTHERS => '0');
+            o_rd_data(24)           <= r_lcd.rw;
+            o_rd_data(31 DOWNTO 25) <= (OTHERS => '0');
+        END IF;
+    END PROCESS p_read;
+
+    pin_o_lcd <= r_lcd;
+
 END ARCHITECTURE a_io_lcd;
 

io/leds.vhd

View file @ fe7741d

@@ -20,18 +20,14 @@ ARCHITECTURE a_io_leds OF e_io_leds IS
 
 BEGIN
 
-    o_rd_data <= r_leds;
-
-    p_write: PROCESS(r_leds, i_wr_data, i_wr_en)
+    p_next: PROCESS(r_leds, i_wr_data, i_wr_en)
     BEGIN
         IF i_wr_en = '1' THEN
             n_leds <= i_wr_data;
         ELSE
             n_leds <= r_leds;
         END IF;
-    END PROCESS p_write;
-
-    pin_o_leds <= r_leds;
+    END PROCESS p_next;
 
     p_sync: PROCESS(rst, clk)
     BEGIN
@@ -42,5 +38,16 @@ BEGIN
         END IF;
     END PROCESS p_sync;
 
+    p_read: PROCESS(rst, clk)
+    BEGIN
+        IF rst = '1' THEN
+            o_rd_data <= (OTHERS => '0');
+        ELSIF rising_edge(clk) THEN
+            o_rd_data <= r_leds;
+        END IF;
+    END PROCESS p_read;
+
+    pin_o_leds <= r_leds;
+
 END ARCHITECTURE a_io_leds;
 


...	...	@@ -19,8 +19,6 @@ ARCHITECTURE a_io_cyc_cnt OF e_io_cyc_cnt IS
19	19
20	20	BEGIN
21	21
22		- o_rd_data <= r_cnt;
23		-
24	22	p_write: PROCESS(r_cnt, i_wr_data, i_wr_en)
25	23	BEGIN
26	24	IF i_wr_en = '1' THEN
...	...	@@ -39,5 +37,14 @@ BEGIN
39	37	END IF;
40	38	END PROCESS p_sync;
41	39
	40	+ p_read: PROCESS(rst, clk)
	41	+ BEGIN
	42	+ IF rst = '1' THEN
	43	+ o_rd_data <= (OTHERS => '0');
	44	+ ELSIF rising_edge(clk) THEN
	45	+ o_rd_data <= r_cnt;
	46	+ END IF;
	47	+ END PROCESS p_read;
	48	+
42	49	END ARCHITECTURE a_io_cyc_cnt;
43	50

...	...	@@ -22,15 +22,7 @@ ARCHITECTURE a_io_lcd OF e_io_lcd IS
22	22
23	23	BEGIN
24	24
25		- o_rd_data( 7 DOWNTO 0) <= r_lcd.data;
26		- o_rd_data( 8) <= r_lcd.e;
27		- o_rd_data(15 DOWNTO 9) <= (OTHERS => '0');
28		- o_rd_data(16) <= r_lcd.rs;
29		- o_rd_data(23 DOWNTO 17) <= (OTHERS => '0');
30		- o_rd_data(24) <= r_lcd.rw;
31		- o_rd_data(31 DOWNTO 25) <= (OTHERS => '0');
32		-
33		- p_write: PROCESS(r_lcd, i_wr_data, i_wr_en)
	25	+ p_next: PROCESS(r_lcd, i_wr_data, i_wr_en)
34	26	BEGIN
35	27	IF i_wr_en(0) = '1' THEN
36	28	n_lcd.data <= i_wr_data(7 DOWNTO 0);
...	...	@@ -52,9 +44,7 @@ BEGIN
52	44	ELSE
53	45	n_lcd.rw <= r_lcd.rw;
54	46	END IF;
55		- END PROCESS p_write;
56		-
57		- pin_o_lcd <= r_lcd;
	47	+ END PROCESS p_next;
58	48
59	49	p_sync: PROCESS(rst, clk)
60	50	BEGIN
...	...	@@ -68,5 +58,22 @@ BEGIN
68	58	END IF;
69	59	END PROCESS p_sync;
70	60
	61	+ p_read: PROCESS(rst, clk)
	62	+ BEGIN
	63	+ IF rst = '1' THEN
	64	+ o_rd_data <= (OTHERS => '0');
	65	+ ELSIF rising_edge(clk) THEN
	66	+ o_rd_data( 7 DOWNTO 0) <= r_lcd.data;
	67	+ o_rd_data( 8) <= r_lcd.e;
	68	+ o_rd_data(15 DOWNTO 9) <= (OTHERS => '0');
	69	+ o_rd_data(16) <= r_lcd.rs;
	70	+ o_rd_data(23 DOWNTO 17) <= (OTHERS => '0');
	71	+ o_rd_data(24) <= r_lcd.rw;
	72	+ o_rd_data(31 DOWNTO 25) <= (OTHERS => '0');
	73	+ END IF;
	74	+ END PROCESS p_read;
	75	+
	76	+ pin_o_lcd <= r_lcd;
	77	+
71	78	END ARCHITECTURE a_io_lcd;
72	79

...	...	@@ -20,18 +20,14 @@ ARCHITECTURE a_io_leds OF e_io_leds IS
20	20
21	21	BEGIN
22	22
23		- o_rd_data <= r_leds;
24		-
25		- p_write: PROCESS(r_leds, i_wr_data, i_wr_en)
	23	+ p_next: PROCESS(r_leds, i_wr_data, i_wr_en)
26	24	BEGIN
27	25	IF i_wr_en = '1' THEN
28	26	n_leds <= i_wr_data;
29	27	ELSE
30	28	n_leds <= r_leds;
31	29	END IF;
32		- END PROCESS p_write;
33		-
34		- pin_o_leds <= r_leds;
	30	+ END PROCESS p_next;
35	31
36	32	p_sync: PROCESS(rst, clk)
37	33	BEGIN
...	...	@@ -42,5 +38,16 @@ BEGIN
42	38	END IF;
43	39	END PROCESS p_sync;
44	40
	41	+ p_read: PROCESS(rst, clk)
	42	+ BEGIN
	43	+ IF rst = '1' THEN
	44	+ o_rd_data <= (OTHERS => '0');
	45	+ ELSIF rising_edge(clk) THEN
	46	+ o_rd_data <= r_leds;
	47	+ END IF;
	48	+ END PROCESS p_read;
	49	+
	50	+ pin_o_leds <= r_leds;
	51	+
45	52	END ARCHITECTURE a_io_leds;
46	53
47	54