MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
added FIFO to UART RX
7f7ba9a @ 2012-02-20 13:36:12
| blocks | added FIFO to UART TX | 2012-02-20 13:00:00 |
|---|---|---|
| constraints | implemented RX part of UART peripheral | 2012-02-20 11:50:59 |
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | added FIFO to UART RX | 2012-02-20 13:36:12 |
| io | added FIFO to UART RX | 2012-02-20 13:36:12 |
| mips | fixed instruction word input on stall, fixed uninitialized instruction word after reset by stalling 1 cycle | 2012-02-16 20:09:51 |
| system | implemented RX part of UART peripheral | 2012-02-20 11:50:59 |
| test | implemented RX part of UART peripheral | 2012-02-20 11:50:59 |
| .gitignore | impact project | 2012-02-11 00:32:06 |
| Default.wcfg | implemented RX part of UART peripheral | 2012-02-20 11:50:59 |
| mips_sys.ipf | impact project | 2012-02-11 00:32:06 |
| mips_sys.xise | added FIFO to UART TX | 2012-02-20 13:00:00 |