add initial values for registers (ea1aa50) - mips_sys · BlinkenArea

add initial values for registers

Stefan Schuermans commited on 2012-02-12 18:05:38
Showing 8 changed files, with 40 additions and 44 deletions.

io/cyc_cnt.vhd 624bd82..7e610ca
io/lcd.vhd d2fd179..47a5125
io/leds.vhd 4ba3309..a25126c
mips/core.vhd d9c10dc..ba7092e
mips/div.vhd 0a0f44a..79256f0
mips/mul_fast.vhd 6f56c1f..c316d74
mips/mul_slow.vhd 59b7eec..222d474
mips/regs.vhd d42c9ed..564d516

io/cyc_cnt.vhd

@@ -15,7 +15,7 @@ END ENTITY e_io_cyc_cnt;
 ARCHITECTURE a_io_cyc_cnt OF e_io_cyc_cnt IS
 
     SIGNAL n_cnt: std_logic_vector(31 DOWNTO 0);
-    SIGNAL r_cnt: std_logic_vector(31 DOWNTO 0);
+    SIGNAL r_cnt: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
 
 BEGIN
 

io/lcd.vhd

View file @ ea1aa50

@@ -17,7 +17,8 @@ END ENTITY e_io_lcd;
 ARCHITECTURE a_io_lcd OF e_io_lcd IS
 
     SIGNAL n_lcd: t_io_lcd_pins;
-    SIGNAL r_lcd: t_io_lcd_pins;
+    SIGNAL r_lcd: t_io_lcd_pins := (data => (OTHERS => '0'),
+                                    e => '0', rs => '0', rw => '0');
 
 BEGIN
 

io/leds.vhd

View file @ ea1aa50

@@ -16,7 +16,7 @@ END ENTITY e_io_leds;
 ARCHITECTURE a_io_leds OF e_io_leds IS
 
     SIGNAL n_leds: std_logic_vector(7 DOWNTO 0);
-    SIGNAL r_leds: std_logic_vector(7 DOWNTO 0);
+    SIGNAL r_leds: std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
 
 BEGIN
 

mips/core.vhd

View file @ ea1aa50

@@ -22,7 +22,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
     SIGNAL s_stall:         std_logic;
     SIGNAL s_stall_data_rd: std_logic;
 
-    SIGNAL r_pc: std_logic_vector(31 DOWNTO 0);
+    SIGNAL r_pc: std_logic_vector(31 DOWNTO 0) := X"FFFFFFFC";
     SIGNAL n_pc: std_logic_vector(31 DOWNTO 0);
 
     SIGNAL s_instr: std_logic_vector(31 DOWNTO 0);
@@ -40,18 +40,18 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
     SIGNAL n_imm:    t_imm;
     SIGNAL n_ldst:   t_ldst;
 
-    SIGNAL r_reg_s:  std_logic_vector( 4 DOWNTO 0);
-    SIGNAL r_reg_t:  std_logic_vector( 4 DOWNTO 0);
-    SIGNAL r_reg_d:  std_logic_vector( 4 DOWNTO 0);
-    SIGNAL r_imm_a:  std_logic_vector( 4 DOWNTO 0);
-    SIGNAL r_imm_16: std_logic_vector(15 DOWNTO 0);
-    SIGNAL r_imm_26: std_logic_vector(25 DOWNTO 0);
-    SIGNAL r_op:     t_op;
-    SIGNAL r_link:   t_link;
-    SIGNAL r_cmp:    t_cmp;
-    SIGNAL r_alu:    t_alu;
-    SIGNAL r_imm:    t_imm;
-    SIGNAL r_ldst:   t_ldst;
+    SIGNAL r_reg_s:  std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_reg_t:  std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_reg_d:  std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_imm_a:  std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_imm_16: std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_imm_26: std_logic_vector(25 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_op:     t_op                          := op_none;
+    SIGNAL r_link:   t_link                        := link_none;
+    SIGNAL r_cmp:    t_cmp                         := cmp_none;
+    SIGNAL r_alu:    t_alu                         := alu_none;
+    SIGNAL r_imm:    t_imm                         := imm_none;
+    SIGNAL r_ldst:   t_ldst                        := ldst_none;
 
     SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
@@ -88,12 +88,12 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
 
     TYPE t_data_rd IS (data_rd_idle, data_rd_read);
     SIGNAL n_data_rd: t_data_rd;
-    SIGNAL r_data_rd: t_data_rd;
+    SIGNAL r_data_rd: t_data_rd := data_rd_idle;
 
     SIGNAL n_reg_lo: std_logic_vector(31 DOWNTO 0);
     SIGNAL n_reg_hi: std_logic_vector(31 DOWNTO 0);
-    SIGNAL r_reg_lo: std_logic_vector(31 DOWNTO 0);
-    SIGNAL r_reg_hi: std_logic_vector(31 DOWNTO 0);
+    SIGNAL r_reg_lo: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_reg_hi: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
 
     SIGNAL s_mul_signed: std_logic;
     SIGNAL s_mul_start:  std_logic;
@@ -126,7 +126,6 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
 
     COMPONENT e_mips_regs IS
         PORT (
-            rst:         IN  std_logic;
             clk:         IN  std_logic;
             i_rd_a_no:   IN  std_logic_vector( 4 DOWNTO 0);
             o_rd_a_data: OUT std_logic_vector(31 DOWNTO 0);
@@ -206,7 +205,6 @@ BEGIN
 
     regs: e_mips_regs
         PORT MAP (
-            rst         => rst,
             clk         => clk,
             i_rd_a_no   => r_reg_s,
             o_rd_a_data => s_val_s,

mips/div.vhd

View file @ ea1aa50

@@ -21,17 +21,17 @@ ARCHITECTURE a_mips_div OF e_mips_div IS
 
     SUBTYPE t_state IS natural RANGE 0 TO 33;
     SIGNAL n_state: t_state;
-    SIGNAL r_state: t_state;
+    SIGNAL r_state: t_state := 0;
 
     SIGNAL n_num:   signed(63 DOWNTO 0);
     SIGNAL n_denom: signed(63 DOWNTO 0);
     SIGNAL n_neg:   boolean;
     SIGNAL n_res:   signed(31 DOWNTO 0);
-    SIGNAL r_num:   signed(63 DOWNTO 0);
-    SIGNAL r_denom: signed(63 DOWNTO 0);
-    SIGNAL r_neg:   boolean;
-    SIGNAL r_res:   signed(31 DOWNTO 0);
-    SIGNAL s_rem:   signed(31 DOWNTO 0);
+    SIGNAL r_num:   signed(63 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_denom: signed(63 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_neg:   boolean             := false;
+    SIGNAL r_res:   signed(31 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL s_rem:   signed(31 DOWNTO 0) := (OTHERS => '0');
 
 BEGIN
 

mips/mul_fast.vhd

View file @ ea1aa50

@@ -20,16 +20,16 @@ ARCHITECTURE a_mips_mul OF e_mips_mul IS
 
     TYPE t_state IS (idle, state_1, state_2, state_3, state_4, post);
     SIGNAL n_state: t_state;
-    SIGNAL r_state: t_state;
+    SIGNAL r_state: t_state := idle;
 
     SIGNAL n_a:   unsigned(31 DOWNTO 0);
     SIGNAL n_b:   unsigned(31 DOWNTO 0);
     SIGNAL n_neg: boolean;
     SIGNAL n_res: unsigned(63 DOWNTO 0);
-    SIGNAL r_a:   unsigned(31 DOWNTO 0);
-    SIGNAL r_b:   unsigned(31 DOWNTO 0);
-    SIGNAL r_res: unsigned(63 DOWNTO 0);
-    SIGNAL r_neg: boolean;
+    SIGNAL r_a:   unsigned(31 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_b:   unsigned(31 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_neg: boolean               := false;
+    SIGNAL r_res: unsigned(63 DOWNTO 0) := (OTHERS => '0');
 
 BEGIN
 

mips/mul_slow.vhd

View file @ ea1aa50

@@ -21,18 +21,18 @@ ARCHITECTURE a_mips_mul OF e_mips_mul IS
     TYPE t_state IS (idle, mul1, add1, mul2, add2, mul3, add3, mul4, add4,
                      post);
     SIGNAL n_state: t_state;
-    SIGNAL r_state: t_state;
+    SIGNAL r_state: t_state := idle;
 
     SIGNAL n_a:   unsigned(31 DOWNTO 0);
     SIGNAL n_b:   unsigned(31 DOWNTO 0);
     SIGNAL n_neg: boolean;
     SIGNAL n_r:   unsigned(31 DOWNTO 0);
     SIGNAL n_res: unsigned(63 DOWNTO 0);
-    SIGNAL r_a:   unsigned(31 DOWNTO 0);
-    SIGNAL r_b:   unsigned(31 DOWNTO 0);
-    SIGNAL r_neg: boolean;
-    SIGNAL r_r:   unsigned(31 DOWNTO 0);
-    SIGNAL r_res: unsigned(63 DOWNTO 0);
+    SIGNAL r_a:   unsigned(31 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_b:   unsigned(31 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_neg: boolean               := false;
+    SIGNAL r_r:   unsigned(31 DOWNTO 0) := (OTHERS => '0');
+    SIGNAL r_res: unsigned(63 DOWNTO 0) := (OTHERS => '0');
 
 BEGIN
 

mips/regs.vhd

View file @ ea1aa50

@@ -5,7 +5,6 @@ USE work.mips_types.all;
 
 ENTITY e_mips_regs IS
     PORT (
-        rst:         IN  std_logic;
         clk:         IN  std_logic;
         i_rd_a_no:   IN  std_logic_vector( 4 DOWNTO 0);
         o_rd_a_data: OUT std_logic_vector(31 DOWNTO 0);
@@ -23,7 +22,7 @@ ARCHITECTURE a_mips_regs OF e_mips_regs IS
 
     TYPE t_regs IS ARRAY(t_idx) OF std_logic_vector(31 DOWNTO 0);
 
-    SIGNAL r_regs: t_regs;
+    SIGNAL r_regs: t_regs := (OTHERS => (OTHERS => '0'));
 
     FUNCTION no2idx(no: std_logic_vector(4 DOWNTO 0)) RETURN natural IS
     BEGIN
@@ -50,11 +49,9 @@ BEGIN
         END IF;
     END PROCESS p_read_b;
 
-    p_write: PROCESS(rst, clk)
+    p_write: PROCESS(clk)
     BEGIN
-        IF rst = '1' THEN
-            -- r_regs <= (OTHERS => X"00000000");
-        ELSIF rising_edge(clk) THEN
+        IF rising_edge(clk) THEN
             IF i_wr_en = '1' THEN
                 r_regs(no2idx(i_wr_no)) <= i_wr_data;
             END IF;


...	...	@@ -15,7 +15,7 @@ END ENTITY e_io_cyc_cnt;
15	15	ARCHITECTURE a_io_cyc_cnt OF e_io_cyc_cnt IS
16	16
17	17	SIGNAL n_cnt: std_logic_vector(31 DOWNTO 0);
18		- SIGNAL r_cnt: std_logic_vector(31 DOWNTO 0);
	18	+ SIGNAL r_cnt: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
19	19
20	20	BEGIN
21	21

...	...	@@ -17,7 +17,8 @@ END ENTITY e_io_lcd;
17	17	ARCHITECTURE a_io_lcd OF e_io_lcd IS
18	18
19	19	SIGNAL n_lcd: t_io_lcd_pins;
20		- SIGNAL r_lcd: t_io_lcd_pins;
	20	+ SIGNAL r_lcd: t_io_lcd_pins := (data => (OTHERS => '0'),
	21	+ e => '0', rs => '0', rw => '0');
21	22
22	23	BEGIN
23	24

...	...	@@ -16,7 +16,7 @@ END ENTITY e_io_leds;
16	16	ARCHITECTURE a_io_leds OF e_io_leds IS
17	17
18	18	SIGNAL n_leds: std_logic_vector(7 DOWNTO 0);
19		- SIGNAL r_leds: std_logic_vector(7 DOWNTO 0);
	19	+ SIGNAL r_leds: std_logic_vector(7 DOWNTO 0) := (OTHERS => '0');
20	20
21	21	BEGIN
22	22

...	...	@@ -22,7 +22,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
22	22	SIGNAL s_stall: std_logic;
23	23	SIGNAL s_stall_data_rd: std_logic;
24	24
25		- SIGNAL r_pc: std_logic_vector(31 DOWNTO 0);
	25	+ SIGNAL r_pc: std_logic_vector(31 DOWNTO 0) := X"FFFFFFFC";
26	26	SIGNAL n_pc: std_logic_vector(31 DOWNTO 0);
27	27
28	28	SIGNAL s_instr: std_logic_vector(31 DOWNTO 0);
...	...	@@ -40,18 +40,18 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
40	40	SIGNAL n_imm: t_imm;
41	41	SIGNAL n_ldst: t_ldst;
42	42
43		- SIGNAL r_reg_s: std_logic_vector( 4 DOWNTO 0);
44		- SIGNAL r_reg_t: std_logic_vector( 4 DOWNTO 0);
45		- SIGNAL r_reg_d: std_logic_vector( 4 DOWNTO 0);
46		- SIGNAL r_imm_a: std_logic_vector( 4 DOWNTO 0);
47		- SIGNAL r_imm_16: std_logic_vector(15 DOWNTO 0);
48		- SIGNAL r_imm_26: std_logic_vector(25 DOWNTO 0);
49		- SIGNAL r_op: t_op;
50		- SIGNAL r_link: t_link;
51		- SIGNAL r_cmp: t_cmp;
52		- SIGNAL r_alu: t_alu;
53		- SIGNAL r_imm: t_imm;
54		- SIGNAL r_ldst: t_ldst;
	43	+ SIGNAL r_reg_s: std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
	44	+ SIGNAL r_reg_t: std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
	45	+ SIGNAL r_reg_d: std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
	46	+ SIGNAL r_imm_a: std_logic_vector( 4 DOWNTO 0) := (OTHERS => '0');
	47	+ SIGNAL r_imm_16: std_logic_vector(15 DOWNTO 0) := (OTHERS => '0');
	48	+ SIGNAL r_imm_26: std_logic_vector(25 DOWNTO 0) := (OTHERS => '0');
	49	+ SIGNAL r_op: t_op := op_none;
	50	+ SIGNAL r_link: t_link := link_none;
	51	+ SIGNAL r_cmp: t_cmp := cmp_none;
	52	+ SIGNAL r_alu: t_alu := alu_none;
	53	+ SIGNAL r_imm: t_imm := imm_none;
	54	+ SIGNAL r_ldst: t_ldst := ldst_none;
55	55
56	56	SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
57	57	SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
...	...	@@ -88,12 +88,12 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
88	88
89	89	TYPE t_data_rd IS (data_rd_idle, data_rd_read);
90	90	SIGNAL n_data_rd: t_data_rd;
91		- SIGNAL r_data_rd: t_data_rd;
	91	+ SIGNAL r_data_rd: t_data_rd := data_rd_idle;
92	92
93	93	SIGNAL n_reg_lo: std_logic_vector(31 DOWNTO 0);
94	94	SIGNAL n_reg_hi: std_logic_vector(31 DOWNTO 0);
95		- SIGNAL r_reg_lo: std_logic_vector(31 DOWNTO 0);
96		- SIGNAL r_reg_hi: std_logic_vector(31 DOWNTO 0);
	95	+ SIGNAL r_reg_lo: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
	96	+ SIGNAL r_reg_hi: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
97	97
98	98	SIGNAL s_mul_signed: std_logic;
99	99	SIGNAL s_mul_start: std_logic;
...	...	@@ -126,7 +126,6 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
126	126
127	127	COMPONENT e_mips_regs IS
128	128	PORT (
129		- rst: IN std_logic;
130	129	clk: IN std_logic;
131	130	i_rd_a_no: IN std_logic_vector( 4 DOWNTO 0);
132	131	o_rd_a_data: OUT std_logic_vector(31 DOWNTO 0);
...	...	@@ -206,7 +205,6 @@ BEGIN
206	205
207	206	regs: e_mips_regs
208	207	PORT MAP (
209		- rst => rst,
210	208	clk => clk,
211	209	i_rd_a_no => r_reg_s,
212	210	o_rd_a_data => s_val_s,

...	...	@@ -21,17 +21,17 @@ ARCHITECTURE a_mips_div OF e_mips_div IS
21	21
22	22	SUBTYPE t_state IS natural RANGE 0 TO 33;
23	23	SIGNAL n_state: t_state;
24		- SIGNAL r_state: t_state;
	24	+ SIGNAL r_state: t_state := 0;
25	25
26	26	SIGNAL n_num: signed(63 DOWNTO 0);
27	27	SIGNAL n_denom: signed(63 DOWNTO 0);
28	28	SIGNAL n_neg: boolean;
29	29	SIGNAL n_res: signed(31 DOWNTO 0);
30		- SIGNAL r_num: signed(63 DOWNTO 0);
31		- SIGNAL r_denom: signed(63 DOWNTO 0);
32		- SIGNAL r_neg: boolean;
33		- SIGNAL r_res: signed(31 DOWNTO 0);
34		- SIGNAL s_rem: signed(31 DOWNTO 0);
	30	+ SIGNAL r_num: signed(63 DOWNTO 0) := (OTHERS => '0');
	31	+ SIGNAL r_denom: signed(63 DOWNTO 0) := (OTHERS => '0');
	32	+ SIGNAL r_neg: boolean := false;
	33	+ SIGNAL r_res: signed(31 DOWNTO 0) := (OTHERS => '0');
	34	+ SIGNAL s_rem: signed(31 DOWNTO 0) := (OTHERS => '0');
35	35
36	36	BEGIN
37	37

...	...	@@ -20,16 +20,16 @@ ARCHITECTURE a_mips_mul OF e_mips_mul IS
20	20
21	21	TYPE t_state IS (idle, state_1, state_2, state_3, state_4, post);
22	22	SIGNAL n_state: t_state;
23		- SIGNAL r_state: t_state;
	23	+ SIGNAL r_state: t_state := idle;
24	24
25	25	SIGNAL n_a: unsigned(31 DOWNTO 0);
26	26	SIGNAL n_b: unsigned(31 DOWNTO 0);
27	27	SIGNAL n_neg: boolean;
28	28	SIGNAL n_res: unsigned(63 DOWNTO 0);
29		- SIGNAL r_a: unsigned(31 DOWNTO 0);
30		- SIGNAL r_b: unsigned(31 DOWNTO 0);
31		- SIGNAL r_res: unsigned(63 DOWNTO 0);
32		- SIGNAL r_neg: boolean;
	29	+ SIGNAL r_a: unsigned(31 DOWNTO 0) := (OTHERS => '0');
	30	+ SIGNAL r_b: unsigned(31 DOWNTO 0) := (OTHERS => '0');
	31	+ SIGNAL r_neg: boolean := false;
	32	+ SIGNAL r_res: unsigned(63 DOWNTO 0) := (OTHERS => '0');
33	33
34	34	BEGIN
35	35

...	...	@@ -21,18 +21,18 @@ ARCHITECTURE a_mips_mul OF e_mips_mul IS
21	21	TYPE t_state IS (idle, mul1, add1, mul2, add2, mul3, add3, mul4, add4,
22	22	post);
23	23	SIGNAL n_state: t_state;
24		- SIGNAL r_state: t_state;
	24	+ SIGNAL r_state: t_state := idle;
25	25
26	26	SIGNAL n_a: unsigned(31 DOWNTO 0);
27	27	SIGNAL n_b: unsigned(31 DOWNTO 0);
28	28	SIGNAL n_neg: boolean;
29	29	SIGNAL n_r: unsigned(31 DOWNTO 0);
30	30	SIGNAL n_res: unsigned(63 DOWNTO 0);
31		- SIGNAL r_a: unsigned(31 DOWNTO 0);
32		- SIGNAL r_b: unsigned(31 DOWNTO 0);
33		- SIGNAL r_neg: boolean;
34		- SIGNAL r_r: unsigned(31 DOWNTO 0);
35		- SIGNAL r_res: unsigned(63 DOWNTO 0);
	31	+ SIGNAL r_a: unsigned(31 DOWNTO 0) := (OTHERS => '0');
	32	+ SIGNAL r_b: unsigned(31 DOWNTO 0) := (OTHERS => '0');
	33	+ SIGNAL r_neg: boolean := false;
	34	+ SIGNAL r_r: unsigned(31 DOWNTO 0) := (OTHERS => '0');
	35	+ SIGNAL r_res: unsigned(63 DOWNTO 0) := (OTHERS => '0');
36	36
37	37	BEGIN
38	38

...	...	@@ -5,7 +5,6 @@ USE work.mips_types.all;
5	5
6	6	ENTITY e_mips_regs IS
7	7	PORT (
8		- rst: IN std_logic;
9	8	clk: IN std_logic;
10	9	i_rd_a_no: IN std_logic_vector( 4 DOWNTO 0);
11	10	o_rd_a_data: OUT std_logic_vector(31 DOWNTO 0);
...	...	@@ -23,7 +22,7 @@ ARCHITECTURE a_mips_regs OF e_mips_regs IS
23	22
24	23	TYPE t_regs IS ARRAY(t_idx) OF std_logic_vector(31 DOWNTO 0);
25	24
26		- SIGNAL r_regs: t_regs;
	25	+ SIGNAL r_regs: t_regs := (OTHERS => (OTHERS => '0'));
27	26
28	27	FUNCTION no2idx(no: std_logic_vector(4 DOWNTO 0)) RETURN natural IS
29	28	BEGIN
...	...	@@ -50,11 +49,9 @@ BEGIN
50	49	END IF;
51	50	END PROCESS p_read_b;
52	51
53		- p_write: PROCESS(rst, clk)
	52	+ p_write: PROCESS(clk)
54	53	BEGIN
55		- IF rst = '1' THEN
56		- -- r_regs <= (OTHERS => X"00000000");
57		- ELSIF rising_edge(clk) THEN
	54	+ IF rising_edge(clk) THEN
58	55	IF i_wr_en = '1' THEN
59	56	r_regs(no2idx(i_wr_no)) <= i_wr_data;
60	57	END IF;
61	58