-
replaced ethernet RX clock domain crossing interface with dual clock FIFO
Stefan Schuermans authored on 2012-03-10 17:43:57
-
fixed uninitialized / not resetted frame done output of ethernet TX frame processing
Stefan Schuermans authored on 2012-03-10 10:56:08
-
send ethernet packet on center button press
Stefan Schuermans authored on 2012-03-07 21:52:08
-
adapt ethernet TX clock timing constraint to transmission of data on falling edge
Stefan Schuermans authored on 2012-03-07 21:18:54
-
transmit data on falling edge of ethernet TX clock
Stefan Schuermans authored on 2012-03-07 21:15:19
-
implemented ethernet RX packet and TX clock in testbed
Stefan Schuermans authored on 2012-03-06 20:48:33
-
implemented ethernet TX interface (not tested yet)
Stefan Schuermans authored on 2012-03-04 21:38:35
-
implemented ethernet RX busmaster -> packet reception working
Stefan Schuermans authored on 2012-03-03 23:42:55
-
converted core to use req and grant signals to access data bus
Stefan Schuermans authored on 2012-03-01 21:23:47
-
changed MIPS core to use read and write ack instead of stall input
Stefan Schuermans authored on 2012-02-29 21:28:37
-
shortcut to switch between HW and simulation config
Stefan Schuermans authored on 2012-02-29 21:28:34
-
add read_enable signal to data bus and some peripherals
Stefan Schuermans authored on 2012-02-26 21:20:53
-
fix reading (1 cycle latency) from ethernet peripheral
Stefan Schuermans authored on 2012-02-26 18:26:02
-
removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy
Stefan Schuermans authored on 2012-02-21 20:40:30
-
begin of ethernet RX implementation, so far only test interface to core, does not meet timing
Stefan Schuermans authored on 2012-02-20 21:16:03