Stefan Schuermans commited on 2012-03-10 17:43:57
Showing 2 changed files, with 56 additions and 79 deletions.
... | ... |
@@ -44,6 +44,7 @@ |
44 | 44 |
<wvobject fp_name="/e_testbed/system/pin_i_eth_rxd" type="array" db_ref_id="1"> |
45 | 45 |
<obj_property name="ElementShortName">pin_i_eth_rxd[4:0]</obj_property> |
46 | 46 |
<obj_property name="ObjectShortName">pin_i_eth_rxd[4:0]</obj_property> |
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+ <obj_property name="Radix">HEXRADIX</obj_property> |
|
47 | 48 |
</wvobject> |
48 | 49 |
<wvobject fp_name="/e_testbed/system/pin_i_eth_rx_dv" type="logic" db_ref_id="1"> |
49 | 50 |
<obj_property name="ElementShortName">pin_i_eth_rx_dv</obj_property> |
... | ... |
@@ -26,21 +26,29 @@ ARCHITECTURE a_io_eth_rxif OF e_io_eth_rxif IS |
26 | 26 |
SIGNAL r_in_state: t_in_state := in_idle; |
27 | 27 |
SIGNAL r_in_data: std_logic_vector(7 DOWNTO 0) := X"00"; |
28 | 28 |
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- TYPE t_if_event IS (if_data, if_done, if_err); |
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- |
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- SIGNAL r_if_rx_clk_trigger: std_logic := '0'; |
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- SIGNAL r_if_rx_clk_event: t_if_event := if_data; |
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- SIGNAL r_if_rx_clk_data: std_logic_vector(7 DOWNTO 0) := X"00"; |
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- |
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- SIGNAL r_if_clk_trigger: std_logic := '0'; |
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- SIGNAL r_if_clk_event: t_if_event := if_data; |
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- SIGNAL r_if_clk_data: std_logic_vector(7 DOWNTO 0) := X"00"; |
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- SIGNAL r_if_clk_en: std_logic := '0'; |
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- |
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- SIGNAL r_out_data: std_logic_vector(7 DOWNTO 0) := X"00"; |
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- SIGNAL r_out_data_en: std_logic := '0'; |
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- SIGNAL r_out_done: std_logic := '0'; |
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- SIGNAL r_out_err: std_logic := '0'; |
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+ SIGNAL s_fifo_wr_rdy: std_logic; |
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+ SIGNAL s_fifo_wr_data: std_logic_vector(9 DOWNTO 0); |
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+ SIGNAL s_fifo_wr_en: std_logic; |
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+ SIGNAL s_fifo_rd_rdy: std_logic; |
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+ SIGNAL s_fifo_rd_data: std_logic_vector(9 DOWNTO 0); |
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+ |
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+ COMPONENT e_block_fifo_dc IS |
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+ GENERIC ( |
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+ addr_width: natural; |
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+ data_width: natural |
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+ ); |
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+ PORT ( |
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+ rst: IN std_logic; |
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+ wr_clk: IN std_logic; |
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+ o_wr_rdy: OUT std_logic; |
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+ i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0); |
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+ i_wr_en: IN std_logic; |
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+ rd_clk: IN std_logic; |
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+ o_rd_rdy: OUT std_logic; |
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+ o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0); |
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+ i_rd_en: IN std_logic |
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+ ); |
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+ END COMPONENT e_block_fifo_dc; |
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BEGIN |
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... | ... |
@@ -114,79 +122,47 @@ BEGIN |
114 | 122 |
END IF; |
115 | 123 |
END PROCESS p_in; |
116 | 124 |
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- p_if_rx_clk: PROCESS(rst, pin_i_rx_clk) |
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+ p_wr_fifo: PROCESS(r_in_state, r_in_data, s_fifo_wr_rdy) |
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BEGIN |
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- IF rst = '1' THEN |
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- r_if_rx_clk_trigger <= '0'; |
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- r_if_rx_clk_event <= if_data; |
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- r_if_rx_clk_data <= X"00"; |
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- ELSIF rising_edge(pin_i_rx_clk) THEN |
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+ s_fifo_wr_data <= (OTHERS => '0'); |
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+ s_fifo_wr_en <= '0'; |
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+ IF s_fifo_wr_rdy = '1' THEN |
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CASE r_in_state IS |
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WHEN in_data => |
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- r_if_rx_clk_trigger <= NOT r_if_rx_clk_trigger; |
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- r_if_rx_clk_event <= if_data; |
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- r_if_rx_clk_data <= r_in_data; |
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+ s_fifo_wr_data(7 DOWNTO 0) <= r_in_data; |
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+ s_fifo_wr_en <= '1'; |
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129 | 134 |
WHEN in_done => |
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- r_if_rx_clk_trigger <= NOT r_if_rx_clk_trigger; |
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- r_if_rx_clk_event <= if_done; |
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+ s_fifo_wr_data(8) <= '1'; |
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+ s_fifo_wr_en <= '1'; |
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WHEN in_err => |
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- r_if_rx_clk_trigger <= NOT r_if_rx_clk_trigger; |
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- r_if_rx_clk_event <= if_err; |
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+ s_fifo_wr_data(9) <= '1'; |
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+ s_fifo_wr_en <= '1'; |
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WHEN OTHERS => NULL; |
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END CASE; |
137 | 142 |
END IF; |
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- END PROCESS p_if_rx_clk; |
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- |
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- p_if_clk: PROCESS(rst, clk) |
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- BEGIN |
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- IF rst = '1' THEN |
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- r_if_clk_trigger <= '0'; |
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- r_if_clk_event <= if_data; |
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- r_if_clk_data <= X"00"; |
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- r_if_clk_en <= '0'; |
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- ELSIF rising_edge(clk) THEN |
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- IF r_if_rx_clk_trigger /= r_if_clk_trigger THEN |
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- r_if_clk_trigger <= NOT r_if_clk_trigger; |
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- r_if_clk_event <= r_if_rx_clk_event; |
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- r_if_clk_data <= r_if_rx_clk_data; |
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- r_if_clk_en <= '1'; |
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- ELSE |
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- r_if_clk_en <= '0'; |
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- END IF; |
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- END IF; |
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- END PROCESS p_if_clk; |
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- |
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- p_out: PROCESS(rst, clk) |
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- BEGIN |
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- IF rst = '1' THEN |
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- r_out_data <= X"00"; |
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- r_out_data_en <= '0'; |
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- r_out_done <= '0'; |
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- r_out_err <= '0'; |
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- ELSIF rising_edge(clk) THEN |
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- r_out_data <= X"00"; |
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- r_out_data_en <= '0'; |
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- r_out_done <= '0'; |
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- r_out_err <= '0'; |
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- IF r_if_clk_en = '1' THEN |
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- CASE r_if_clk_event IS |
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- WHEN if_data => |
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- r_out_data <= r_if_clk_data; |
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- r_out_data_en <= '1'; |
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- WHEN if_done => |
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- r_out_done <= '1'; |
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- WHEN if_err => |
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- r_out_err <= '1'; |
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- WHEN OTHERS => NULL; |
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- END CASE; |
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- END IF; |
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- END IF; |
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- END PROCESS p_out; |
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+ END PROCESS p_wr_fifo; |
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+ |
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+ fifo: e_block_fifo_dc |
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+ GENERIC MAP ( |
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+ addr_width => 2, |
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+ data_width => 10 |
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+ ) |
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+ PORT MAP ( |
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+ rst => rst, |
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+ wr_clk => pin_i_rx_clk, |
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+ o_wr_rdy => s_fifo_wr_rdy, |
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+ i_wr_data => s_fifo_wr_data, |
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+ i_wr_en => s_fifo_wr_en, |
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+ rd_clk => clk, |
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+ o_rd_rdy => s_fifo_rd_rdy, |
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+ o_rd_data => s_fifo_rd_data, |
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+ i_rd_en => s_fifo_rd_rdy |
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+ ); |
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- o_data <= r_out_data; |
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- o_data_en <= r_out_data_en; |
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- o_done <= r_out_done; |
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- o_err <= r_out_err; |
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+ o_data <= s_fifo_rd_data(7 DOWNTO 0); |
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+ o_data_en <= s_fifo_rd_rdy; |
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+ o_done <= s_fifo_rd_data(8); |
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+ o_err <= s_fifo_rd_data(9); |
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190 | 166 |
|
191 | 167 |
END ARCHITECTURE a_io_eth_rxif; |
192 | 168 |
|
193 | 169 |