mips_sys

fixed FIFO implementation
Parent 3c3bec9
Stefan Schuermans

Stefan Schuermans commited on 2012-03-06 20:47:36
Showing 1 changed files, with 4 additions and 4 deletions.

blocks/fifo.vhd
View file @ 230fe3b
... ... 
@@ -70,7 +70,7 @@ BEGIN
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     s_ram_rd_addr <= std_logic_vector(to_unsigned(r_begin, addr_width));
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-    s_rd_rdy <= '0' WHEN r_begin = r_end OR r_begin_chgd = '1' ELSE '1';
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+    s_rd_rdy <= '0' WHEN r_begin = r_end_dly2 OR r_begin_chgd = '1' ELSE '1';
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     s_wr_rdy <= '0' WHEN r_begin = next_pos(r_end)                  ELSE '1';
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     o_rd_rdy <= s_rd_rdy;
... ... 
@@ -114,13 +114,13 @@ BEGIN
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                 r_ram_wr_addr <= std_logic_vector(to_unsigned(r_end, addr_width));
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                 r_ram_wr_data <= i_wr_data;
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                 r_ram_wr_en   <= '1';
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-                r_end_dly2    <= next_pos(r_end);
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+                r_end         <= next_pos(r_end);
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             ELSE
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                 r_ram_wr_en  <= '0';
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             END IF;
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             -- delay r_end 2 cycles: 1 for writing to RAM, 1 to read RAM
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-            r_end_dly1 <= r_end_dly2;
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-            r_end      <= r_end_dly1;
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+            r_end_dly1 <= r_end;
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+            r_end_dly2 <= r_end_dly1;
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         END IF;
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     END PROCESS p_fifo;
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