MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
blocks | fixed FIFO implementation | 2012-03-06 20:47:36 |
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constraints | timing for ethernet clocks | 2012-02-21 21:39:56 |
doc | MIPS ISA spec | 2012-01-24 21:41:27 |
fw | implemented ethernet TX firmware | 2012-03-06 18:59:32 |
io | transmit data on falling edge of ethernet TX clock | 2012-03-07 21:15:19 |
mips | converted core to use req and grant signals to access data bus | 2012-03-01 21:23:47 |
stuff | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
system | implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) | 2012-03-05 22:01:56 |
test | implemented ethernet RX packet and TX clock in testbed | 2012-03-06 20:48:33 |
.gitignore | impact project | 2012-02-11 00:32:06 |
Default.wcfg | implemented ethernet RX packet and TX clock in testbed | 2012-03-06 20:48:33 |
mips_sys.ipf | impact project | 2012-02-11 00:32:06 |
mips_sys.xise | implemented ethernet RX packet and TX clock in testbed | 2012-03-06 20:48:33 |