mips_sys

transmit data on falling edge of ethernet TX clock
Parent 6f152d9
Stefan Schuermans

Stefan Schuermans commited on 2012-03-07 21:15:19
Showing 1 changed files, with 1 additions and 1 deletions.

io/eth/txif.vhd
View file @ e31652f
... ... 
@@ -40,7 +40,7 @@ BEGIN
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         IF rst = '1' THEN
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             pin_o_txd   <= X"0";
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             pin_o_tx_en <= '0';
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-        ELSIF rising_edge(pin_i_tx_clk) THEN
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+        ELSIF falling_edge(pin_i_tx_clk) THEN
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             CASE r_out_state IS
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                 WHEN out_idle =>
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                     pin_o_txd   <= X"0";
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