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adapt ethernet TX clock timing constraint to transmission of data on falling edge
Stefan Schuermans authored on 2012-03-07 21:18:54
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transmit data on falling edge of ethernet TX clock
Stefan Schuermans authored on 2012-03-07 21:15:19
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implemented ethernet RX packet and TX clock in testbed
Stefan Schuermans authored on 2012-03-06 20:48:33
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implemented ethernet TX interface (not tested yet)
Stefan Schuermans authored on 2012-03-04 21:38:35
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implemented ethernet RX busmaster -> packet reception working
Stefan Schuermans authored on 2012-03-03 23:42:55
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converted core to use req and grant signals to access data bus
Stefan Schuermans authored on 2012-03-01 21:23:47
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changed MIPS core to use read and write ack instead of stall input
Stefan Schuermans authored on 2012-02-29 21:28:37
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shortcut to switch between HW and simulation config
Stefan Schuermans authored on 2012-02-29 21:28:34
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add read_enable signal to data bus and some peripherals
Stefan Schuermans authored on 2012-02-26 21:20:53
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fix reading (1 cycle latency) from ethernet peripheral
Stefan Schuermans authored on 2012-02-26 18:26:02
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removed bottleneck from data bus implementation, now meets timing even with keep_hierarchy
Stefan Schuermans authored on 2012-02-21 20:40:30
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begin of ethernet RX implementation, so far only test interface to core, does not meet timing
Stefan Schuermans authored on 2012-02-20 21:16:03
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increased code and data address range to 8KB
Stefan Schuermans authored on 2012-02-20 15:55:19
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fixed instruction word input on stall, fixed uninitialized instruction word after reset by stalling 1 cycle
Stefan Schuermans authored on 2012-02-16 20:09:51
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implemented displaying rotary counter (octal)
Stefan Schuermans authored on 2012-02-12 21:51:32
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read peripherals with one cycle delay - as for memory
Stefan Schuermans authored on 2012-02-12 19:10:11
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converted code to use constants in data memory
Stefan Schuermans authored on 2012-02-12 18:24:53
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implemented loading of data memory from firmware
Stefan Schuermans authored on 2012-02-12 17:47:50
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slower LED animation for execution on FPGA
Stefan Schuermans authored on 2012-02-11 00:31:59
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clock and reset constraints are for whole system
Stefan Schuermans authored on 2012-02-10 23:22:30
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if not comparing, jump is unconditional, so compare must return true
Stefan Schuermans authored on 2012-02-10 22:45:59
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implented basic system with core, instr memory, data memory
Stefan Schuermans authored on 2012-02-06 21:28:00
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second version of multiplier (slower, i.e. more stages -> faster clock)
Stefan Schuermans authored on 2012-02-05 21:39:45
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implemented ... and link -> MIPSel1 core complete
Stefan Schuermans authored on 2012-02-05 21:16:11
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decoding MULT(U)/DIV(U) -> MIPSel1 decoder complete
Stefan Schuermans authored on 2012-02-05 17:32:53
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implemented simple store instructions, preparations for load instructions
Stefan Schuermans authored on 2012-02-05 13:58:17
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implemented "register 0 is always 0" in a faster way
Stefan Schuermans authored on 2012-01-26 21:17:30
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implement jump logic, implement instruction fetch
Stefan Schuermans authored on 2012-01-25 23:17:28
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implement correctly writing to register file
Stefan Schuermans authored on 2012-01-24 21:52:18
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start of MIPS core: begin of decoder and ALU
Stefan Schuermans authored on 2012-01-23 22:06:18