implemented LCD peripheral (df6d296) - mips_sys · BlinkenArea

implemented LCD peripheral

Stefan Schuermans commited on 2012-02-12 15:31:45
Showing 13 changed files, with 384 additions and 23 deletions.

Default.wcfg e74e728..4e62302
constraints/lcd.ucf 0000000..61c5d2c
fw/Makefile 0d5c75e..214a772
fw/cyc_cnt.c 1ad4e96..140824b
fw/cyc_cnt.h 9875952..6f75907
fw/lcd.c 0000000..25b54e0
fw/lcd.h 0000000..2f5ab40
fw/main.c 0f735b6..a9b7f38
io/lcd.vhd 0000000..d2fd179
io/lcd_pins.vhd 0000000..adef9bf
mips_sys.xise 31658b4..9539236
system/system.vhd 6873cec..29f9050
test/testbed.vhd 5f56322..ab6db10

Default.wcfg

@@ -6,6 +6,7 @@
       <db_ref path="/home/stefan/spartan3/mips_sys/e_testbed_isim_beh.wdb" id="1" type="auto">
          <top_modules>
             <top_module name="e_testbed" />
+            <top_module name="io_lcd_pins" />
             <top_module name="mips_types" />
             <top_module name="numeric_std" />
             <top_module name="std_logic_1164" />
@@ -13,7 +14,7 @@
          </top_modules>
       </db_ref>
    </db_ref_list>
-   <WVObjectSize size="25" />
+   <WVObjectSize size="26" />
    <wvobject fp_name="/e_testbed/s_rst" type="logic" db_ref_id="1">
       <obj_property name="ElementShortName">s_rst</obj_property>
       <obj_property name="ObjectShortName">s_rst</obj_property>
@@ -26,6 +27,10 @@
       <obj_property name="ElementShortName">pin_leds[7:0]</obj_property>
       <obj_property name="ObjectShortName">pin_leds[7:0]</obj_property>
    </wvobject>
+   <wvobject fp_name="/e_testbed/pin_lcd" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">pin_lcd</obj_property>
+      <obj_property name="ObjectShortName">pin_lcd</obj_property>
+   </wvobject>
    <wvobject fp_name="/e_testbed/system/core/regs/r_regs[29]" type="array" db_ref_id="1">
       <obj_property name="ElementShortName">[29]</obj_property>
       <obj_property name="ObjectShortName">r_regs[29]</obj_property>

constraints/lcd.ucf

View file @ df6d296

...	...	@@ -0,0 +1,11 @@
	1	+NET "pin_o_lcd_data[7]" LOC = "Y15" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	2	+NET "pin_o_lcd_data[6]" LOC = "AB16" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	3	+NET "pin_o_lcd_data[5]" LOC = "Y16" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	4	+NET "pin_o_lcd_data[4]" LOC = "AA12" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	5	+NET "pin_o_lcd_data[3]" LOC = "AB12" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	6	+NET "pin_o_lcd_data[2]" LOC = "AB17" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	7	+NET "pin_o_lcd_data[1]" LOC = "AB18" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	8	+NET "pin_o_lcd_data[0]" LOC = "Y13" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	9	+NET "pin_o_lcd_e" LOC = "AB4" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	10	+NET "pin_o_lcd_rs" LOC = "Y14" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	11	+NET "pin_o_lcd_rw" LOC = "W13" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;

fw/Makefile

View file @ df6d296

...	...	@@ -1,4 +1,4 @@
1		-SRCS=cyc_cnt.c leds.c main.c
	1	+SRCS=cyc_cnt.c lcd.c leds.c main.c
2	2
3	3	CC=mipsel-elf-gcc
4	4	LD=mipsel-elf-ld

fw/cyc_cnt.c

View file @ df6d296

...	...	@@ -10,3 +10,32 @@ unsigned int cyc_cnt_read(void)
10	10	return *p_cyc_cnt;
11	11	}
12	12
	13	+/**
	14	+ * @brief delay for a number of cycles
	15	+ * @param[in] cyc number of cycles
	16	+ */
	17	+void cyc_cnt_delay(unsigned int cyc)
	18	+{
	19	+ unsigned int start = cyc_cnt_read();
	20	+ while (cyc_cnt_read() - start < cyc)
	21	+ /* wait */;
	22	+}
	23	+
	24	+/**
	25	+ * @brief delay for a number of microseconds
	26	+ * @param[in] us number of microseconds
	27	+ */
	28	+void cyc_cnt_delay_us(unsigned int us)
	29	+{
	30	+ cyc_cnt_delay(us * 50);
	31	+}
	32	+
	33	+/**
	34	+ * @brief delay for a number of milliseconds
	35	+ * @param[in] ms number of milliseconds
	36	+ */
	37	+void cyc_cnt_delay_ms(unsigned int ms)
	38	+{
	39	+ cyc_cnt_delay_us(ms * 1000);
	40	+}
	41	+

fw/cyc_cnt.h

View file @ df6d296

@@ -7,5 +7,23 @@
  */
 unsigned int cyc_cnt_read(void);
 
+/**
+ * @brief delay for a number of cycles
+ * @param[in] cyc number of cycles
+ */
+void cyc_cnt_delay(unsigned int cyc);
+
+/**
+ * @brief delay for a number of microseconds
+ * @param[in] us number of microseconds
+ */
+void cyc_cnt_delay_us(unsigned int us);
+
+/**
+ * @brief delay for a number of milliseconds
+ * @param[in] ms number of milliseconds
+ */
+void cyc_cnt_delay_ms(unsigned int ms);
+
 #endif /* #ifndef CYC_CNT_H */
 

fw/lcd.c

View file @ df6d296

...	...	@@ -0,0 +1,116 @@
	1	+#include "cyc_cnt.h"
	2	+#include "lcd.h"
	3	+
	4	+/**
	5	+ * @brief set data to LCD
	6	+ * @param[in] data data to LCD
	7	+ */
	8	+void lcd_set_data(unsigned char data)
	9	+{
	10	+ volatile unsigned char p_lcd_d = (volatile unsigned char )0x80000100;
	11	+ *p_lcd_d = data;
	12	+}
	13	+
	14	+/**
	15	+ * @brief set enable signal to LCD
	16	+ * @param[in] state state for enable signal (0 or 1)
	17	+ */
	18	+void lcd_set_e(unsigned char state)
	19	+{
	20	+ volatile unsigned char p_lcd_e = (volatile unsigned char )0x80000101;
	21	+ *p_lcd_e = state;
	22	+}
	23	+
	24	+/**
	25	+ * @brief set register select signal to LCD
	26	+ * @param[in] state state for register select signal (0 or 1)
	27	+ */
	28	+void lcd_set_rs(unsigned char state)
	29	+{
	30	+ volatile unsigned char p_lcd_rs = (volatile unsigned char )0x80000102;
	31	+ *p_lcd_rs = state;
	32	+}
	33	+
	34	+/**
	35	+ * @brief set read/write signal to LCD
	36	+ * @param[in] state state for read/write signal (0 or 1)
	37	+ */
	38	+void lcd_set_rw(unsigned char state)
	39	+{
	40	+ volatile unsigned char p_lcd_rw = (volatile unsigned char )0x80000103;
	41	+ *p_lcd_rw = state;
	42	+}
	43	+
	44	+/** set LCD to 4 bit mode */
	45	+void lcd_set4bit(void)
	46	+{
	47	+ lcd_set_data(0x0F);
	48	+ lcd_set_e(0);
	49	+ lcd_set_rs(0);
	50	+ lcd_set_rw(0);
	51	+ cyc_cnt_delay_ms(15);
	52	+ lcd_set_data(0x3F);
	53	+ lcd_set_e(1);
	54	+ cyc_cnt_delay(12);
	55	+ lcd_set_e(0);
	56	+ cyc_cnt_delay_us(4100);
	57	+ lcd_set_e(1);
	58	+ cyc_cnt_delay(12);
	59	+ lcd_set_e(0);
	60	+ cyc_cnt_delay_us(100);
	61	+ lcd_set_e(1);
	62	+ cyc_cnt_delay(12);
	63	+ lcd_set_e(0);
	64	+ cyc_cnt_delay_us(40);
	65	+ lcd_set_data(0x2F);
	66	+ lcd_set_e(1);
	67	+ cyc_cnt_delay(12);
	68	+ lcd_set_e(0);
	69	+ cyc_cnt_delay_us(40);
	70	+}
	71	+
	72	+/**
	73	+ * @brief output a byte to LCD
	74	+ * @param[in] data if the byte is a data byte (command otherwise)
	75	+ * @param[in] byte byte to write
	76	+ */
	77	+void lcd_byte(unsigned char data, unsigned char byte)
	78	+{
	79	+ lcd_set_e(0);
	80	+ lcd_set_rs(data ? 1: 0);
	81	+ lcd_set_rw(0);
	82	+ lcd_set_data(byte \| 0x0F);
	83	+ lcd_set_e(1);
	84	+ cyc_cnt_delay(12);
	85	+ lcd_set_e(0);
	86	+ cyc_cnt_delay_us(1);
	87	+ lcd_set_data(byte << 4 \| 0x0F);
	88	+ lcd_set_e(1);
	89	+ cyc_cnt_delay(12);
	90	+ lcd_set_e(0);
	91	+ cyc_cnt_delay_us(40);
	92	+}
	93	+
	94	+/** initialize LCD */
	95	+void lcd_init(void)
	96	+{
	97	+ lcd_set4bit();
	98	+ lcd_byte(0, 0x28);
	99	+ lcd_byte(0, 0x06);
	100	+ lcd_byte(0, 0x0C);
	101	+ lcd_byte(0, 0x01);
	102	+ cyc_cnt_delay_us(1640);
	103	+ lcd_byte(1, 'H');
	104	+ lcd_byte(1, 'e');
	105	+ lcd_byte(1, 'l');
	106	+ lcd_byte(1, 'l');
	107	+ lcd_byte(1, 'o');
	108	+ lcd_byte(1, ' ');
	109	+ lcd_byte(1, 'W');
	110	+ lcd_byte(1, 'o');
	111	+ lcd_byte(1, 'r');
	112	+ lcd_byte(1, 'l');
	113	+ lcd_byte(1, 'd');
	114	+ lcd_byte(1, '!');
	115	+}
	116	+

fw/lcd.h

View file @ df6d296

...	...	@@ -0,0 +1,42 @@
	1	+#ifndef LCD_H
	2	+#define LCD_H
	3	+
	4	+/**
	5	+ * @brief set data to LCD
	6	+ * @param[in] data data to LCD
	7	+ */
	8	+void lcd_set_data(unsigned char data);
	9	+
	10	+/**
	11	+ * @brief set enable signal to LCD
	12	+ * @param[in] state state for enable signal (0 or 1)
	13	+ */
	14	+void lcd_set_e(unsigned char state);
	15	+
	16	+/**
	17	+ * @brief set register select signal to LCD
	18	+ * @param[in] state state for register select signal (0 or 1)
	19	+ */
	20	+void lcd_set_rs(unsigned char state);
	21	+
	22	+/**
	23	+ * @brief set read/write signal to LCD
	24	+ * @param[in] state state for read/write signal (0 or 1)
	25	+ */
	26	+void lcd_set_rw(unsigned char state);
	27	+
	28	+/** set LCD to 4 bit mode */
	29	+void lcd_set4bit(void);
	30	+
	31	+/**
	32	+ * @brief output a byte to LCD
	33	+ * @param[in] data if the byte is a data byte (command otherwise)
	34	+ * @param[in] byte byte to write
	35	+ */
	36	+void lcd_byte(unsigned char data, unsigned char byte);
	37	+
	38	+/** initialize LCD */
	39	+void lcd_init(void);
	40	+
	41	+#endif /* #ifndef LCD_H */
	42	+

fw/main.c

View file @ df6d296

@@ -1,13 +1,12 @@
 #include "cyc_cnt.h"
+#include "lcd.h"
 #include "leds.h"
 
 volatile int data[100];
 
-void delay()
+void delay(void)
 {
-  unsigned int start = cyc_cnt_read();
-  while (cyc_cnt_read() - start < 10000000)
-    /* wait */;
+  cyc_cnt_delay_ms(200);
 }
 
 int main()
@@ -17,6 +16,8 @@ int main()
   for (i = 0; i < sizeof(data) / sizeof(data[0]); ++i)
     data[i] = i;
 
+  lcd_init();
+
   while (1) {
     for (i = 0x1; i < 0x80; i <<= 1) {
       leds_set_state(i);

io/lcd.vhd

View file @ df6d296

...	...	@@ -0,0 +1,71 @@
	1	+LIBRARY IEEE;
	2	+USE IEEE.STD_LOGIC_1164.ALL;
	3	+USE IEEE.NUMERIC_STD.ALL;
	4	+USE work.io_lcd_pins.all;
	5	+
	6	+ENTITY e_io_lcd IS
	7	+ PORT (
	8	+ rst: IN std_logic;
	9	+ clk: IN std_logic;
	10	+ o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
	11	+ i_wr_data: IN std_logic_vector(31 DOWNTO 0);
	12	+ i_wr_en: IN std_logic_vector( 3 DOWNTO 0);
	13	+ pin_o_lcd: OUT t_io_lcd_pins
	14	+ );
	15	+END ENTITY e_io_lcd;
	16	+
	17	+ARCHITECTURE a_io_lcd OF e_io_lcd IS
	18	+
	19	+ SIGNAL n_lcd: t_io_lcd_pins;
	20	+ SIGNAL r_lcd: t_io_lcd_pins;
	21	+
	22	+BEGIN
	23	+
	24	+ o_rd_data( 7 DOWNTO 0) <= r_lcd.data;
	25	+ o_rd_data( 8) <= r_lcd.e;
	26	+ o_rd_data(15 DOWNTO 9) <= (OTHERS => '0');
	27	+ o_rd_data(16) <= r_lcd.rs;
	28	+ o_rd_data(23 DOWNTO 17) <= (OTHERS => '0');
	29	+ o_rd_data(24) <= r_lcd.rw;
	30	+ o_rd_data(31 DOWNTO 25) <= (OTHERS => '0');
	31	+
	32	+ p_write: PROCESS(r_lcd, i_wr_data, i_wr_en)
	33	+ BEGIN
	34	+ IF i_wr_en(0) = '1' THEN
	35	+ n_lcd.data <= i_wr_data(7 DOWNTO 0);
	36	+ ELSE
	37	+ n_lcd.data <= r_lcd.data;
	38	+ END IF;
	39	+ IF i_wr_en(1) = '1' THEN
	40	+ n_lcd.e <= i_wr_data(8);
	41	+ ELSE
	42	+ n_lcd.e <= r_lcd.e;
	43	+ END IF;
	44	+ IF i_wr_en(2) = '1' THEN
	45	+ n_lcd.rs <= i_wr_data(16);
	46	+ ELSE
	47	+ n_lcd.rs <= r_lcd.rs;
	48	+ END IF;
	49	+ IF i_wr_en(3) = '1' THEN
	50	+ n_lcd.rw <= i_wr_data(24);
	51	+ ELSE
	52	+ n_lcd.rw <= r_lcd.rw;
	53	+ END IF;
	54	+ END PROCESS p_write;
	55	+
	56	+ pin_o_lcd <= r_lcd;
	57	+
	58	+ p_sync: PROCESS(rst, clk)
	59	+ BEGIN
	60	+ IF rst = '1' THEN
	61	+ r_lcd.data <= (OTHERS => '0');
	62	+ r_lcd.e <= '0';
	63	+ r_lcd.rs <= '0';
	64	+ r_lcd.rw <= '0';
	65	+ ELSIF rising_edge(clk) THEN
	66	+ r_lcd <= n_lcd;
	67	+ END IF;
	68	+ END PROCESS p_sync;
	69	+
	70	+END ARCHITECTURE a_io_lcd;
	71	+

io/lcd_pins.vhd

View file @ df6d296

...	...	@@ -0,0 +1,16 @@
	1	+LIBRARY ieee;
	2	+USE ieee.std_logic_1164.all;
	3	+USE ieee.numeric_std.all;
	4	+
	5	+PACKAGE io_lcd_pins IS
	6	+
	7	+ TYPE t_io_lcd_pins IS
	8	+ RECORD
	9	+ data: std_logic_vector(7 DOWNTO 0);
	10	+ e: std_logic;
	11	+ rs: std_logic;
	12	+ rw: std_logic;
	13	+ END RECORD;
	14	+
	15	+END PACKAGE io_lcd_pins;
	16	+

mips_sys.xise

View file @ df6d296

@@ -28,8 +28,8 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
@@ -52,26 +52,26 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="system/ram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
     </file>
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -83,8 +83,19 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+    </file>
+    <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+    </file>
+    <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+    </file>
+    <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
 
@@ -208,6 +219,7 @@
     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Selected UCF File" xil_pn:value="/home/stefan/spartan3/mips_sys/constraints/lcd.ucf" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
@@ -321,7 +333,7 @@
     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="100 us" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
@@ -400,6 +412,7 @@
     <binding xil_pn:location="/e_system" xil_pn:name="constraints/leds.ucf"/>
     <binding xil_pn:location="/e_system" xil_pn:name="constraints/clk.ucf"/>
     <binding xil_pn:location="/e_system" xil_pn:name="constraints/rst.ucf"/>
+    <binding xil_pn:location="/e_system" xil_pn:name="constraints/lcd.ucf"/>
   </bindings>
 
   <libraries/>

system/system.vhd

View file @ df6d296

@@ -1,12 +1,14 @@
 LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
+USE work.io_lcd_pins.all;
 
 ENTITY e_system IS
     PORT (
         rst:        IN  std_logic;
         clk:        IN  std_logic;
-        pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
+        pin_o_leds: OUT std_logic_vector(7 DOWNTO 0);
+        pin_o_lcd:  OUT t_io_lcd_pins
     );
 END ENTITY e_system;
 
@@ -25,6 +27,9 @@ ARCHITECTURE a_system OF e_system IS
     SIGNAL s_leds_rd_data: std_logic_vector( 7 DOWNTO 0);
     SIGNAL s_leds_wr_data: std_logic_vector( 7 DOWNTO 0);
     SIGNAL s_leds_wr_en:   std_logic;
+    SIGNAL s_lcd_rd_data: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_lcd_wr_data: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_lcd_wr_en:   std_logic_vector( 3 DOWNTO 0);
     SIGNAL s_cyc_cnt_rd_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_cyc_cnt_wr_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_cyc_cnt_wr_en:   std_logic;
@@ -79,6 +84,17 @@ ARCHITECTURE a_system OF e_system IS
         );
     END COMPONENT e_io_leds;
 
+    COMPONENT e_io_lcd IS
+        PORT (
+            rst:       IN  std_logic;
+            clk:       IN  std_logic;
+            o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
+            i_wr_data: IN  std_logic_vector(31 DOWNTO 0);
+            i_wr_en:   IN  std_logic_vector( 3 DOWNTO 0);
+            pin_o_lcd: OUT t_io_lcd_pins
+        );
+    END COMPONENT e_io_lcd;
+
     COMPONENT e_io_cyc_cnt IS
         PORT (
             rst:       IN  std_logic;
@@ -117,6 +133,7 @@ BEGIN
     p_dbus: PROCESS(s_dbus_addr, s_dbus_wr_data, s_dbus_wr_en,
                     s_data_rd_data,
                     s_leds_rd_data,
+                    s_lcd_rd_data,
                     s_cyc_cnt_rd_data)
         VARIABLE v_wr_en_word: std_logic;
     BEGIN
@@ -128,6 +145,10 @@ BEGIN
         s_data_wr_en   <= (OTHERS => '0');
         s_leds_wr_data <= (OTHERS => '0');
         s_leds_wr_en   <= '0';
+        s_lcd_wr_data <= (OTHERS => '0');
+        s_lcd_wr_en   <= (OTHERS => '0');
+        s_cyc_cnt_wr_data <= (OTHERS => '0');
+        s_cyc_cnt_wr_en   <= '0';
         IF s_dbus_addr(31) = '0' THEN
             s_dbus_rd_data <= s_data_rd_data;
             s_data_addr    <= s_dbus_addr;
@@ -139,6 +160,10 @@ BEGIN
                     s_dbus_rd_data <= X"000000" & s_leds_rd_data;
                     s_leds_wr_data <= s_dbus_wr_data(7 DOWNTO 0);
                     s_leds_wr_en   <= s_dbus_wr_en(0);
+                WHEN X"01" =>
+                    s_dbus_rd_data <= s_lcd_rd_data;
+                    s_lcd_wr_data  <= s_dbus_wr_data;
+                    s_lcd_wr_en    <= s_dbus_wr_en;
                 WHEN X"10" =>
                     s_dbus_rd_data    <= s_cyc_cnt_rd_data;
                     s_cyc_cnt_wr_data <= s_dbus_wr_data;
@@ -173,6 +198,16 @@ BEGIN
             pin_o_leds => pin_o_leds
         );
 
+    lcd: e_io_lcd
+        PORT MAP (
+            rst       => rst,
+            clk       => clk,
+            o_rd_data => s_lcd_rd_data,
+            i_wr_data => s_lcd_wr_data,
+            i_wr_en   => s_lcd_wr_en,
+            pin_o_lcd => pin_o_lcd
+        );
+
     cyc_cnt: e_io_cyc_cnt
         PORT MAP (
             rst       => rst,

test/testbed.vhd

View file @ df6d296

@@ -2,6 +2,7 @@ LIBRARY ieee;
 USE ieee.std_logic_1164.all;
 USE ieee.numeric_std.all;
 USE std.textio.all;
+USE work.io_lcd_pins.all;
 
 ENTITY e_testbed IS
 END ENTITY e_testbed;
@@ -12,13 +13,15 @@ ARCHITECTURE a_testbed OF e_testbed IS
         PORT (
             rst:        IN  std_logic;
             clk:        IN  std_logic;
-            pin_o_leds:   OUT std_logic_vector(7 DOWNTO 0)
+            pin_o_leds: OUT std_logic_vector(7 DOWNTO 0);
+            pin_o_lcd:  OUT t_io_lcd_pins
         );
     END COMPONENT e_system;
 
     SIGNAL s_rst:    std_logic;
     SIGNAL s_clk:    std_logic;
     SIGNAL pin_leds: std_logic_vector(7 DOWNTO 0);
+    SIGNAL pin_lcd:  t_io_lcd_pins;
 
 BEGIN
 
@@ -26,7 +29,8 @@ BEGIN
         PORT MAP (
             clk        => s_clk,
             rst        => s_rst,
-            pin_o_leds => pin_leds
+            pin_o_leds => pin_leds,
+            pin_o_lcd  => pin_lcd
         );
 
     p_rst_clk: PROCESS


...	...	@@ -0,0 +1,11 @@
	1	+NET "pin_o_lcd_data[7]" LOC = "Y15" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	2	+NET "pin_o_lcd_data[6]" LOC = "AB16" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	3	+NET "pin_o_lcd_data[5]" LOC = "Y16" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	4	+NET "pin_o_lcd_data[4]" LOC = "AA12" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	5	+NET "pin_o_lcd_data[3]" LOC = "AB12" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	6	+NET "pin_o_lcd_data[2]" LOC = "AB17" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	7	+NET "pin_o_lcd_data[1]" LOC = "AB18" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	8	+NET "pin_o_lcd_data[0]" LOC = "Y13" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	9	+NET "pin_o_lcd_e" LOC = "AB4" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	10	+NET "pin_o_lcd_rs" LOC = "Y14" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;
	11	+NET "pin_o_lcd_rw" LOC = "W13" \| IOSTANDARD = LVCMOS33 \| DRIVE = 4 \| SLEW = QUIETIO;

...	...	@@ -6,6 +6,7 @@
6	6	<db_ref path="/home/stefan/spartan3/mips_sys/e_testbed_isim_beh.wdb" id="1" type="auto">
7	7	<top_modules>
8	8	<top_module name="e_testbed" />
	9	+ <top_module name="io_lcd_pins" />
9	10	<top_module name="mips_types" />
10	11	<top_module name="numeric_std" />
11	12	<top_module name="std_logic_1164" />
...	...	@@ -13,7 +14,7 @@
13	14	</top_modules>
14	15	</db_ref>
15	16	</db_ref_list>
16		- <WVObjectSize size="25" />
	17	+ <WVObjectSize size="26" />
17	18	<wvobject fp_name="/e_testbed/s_rst" type="logic" db_ref_id="1">
18	19	<obj_property name="ElementShortName">s_rst</obj_property>
19	20	<obj_property name="ObjectShortName">s_rst</obj_property>
...	...	@@ -26,6 +27,10 @@
26	27	<obj_property name="ElementShortName">pin_leds[7:0]</obj_property>
27	28	<obj_property name="ObjectShortName">pin_leds[7:0]</obj_property>
28	29	</wvobject>
	30	+ <wvobject fp_name="/e_testbed/pin_lcd" type="array" db_ref_id="1">
	31	+ <obj_property name="ElementShortName">pin_lcd</obj_property>
	32	+ <obj_property name="ObjectShortName">pin_lcd</obj_property>
	33	+ </wvobject>
29	34	<wvobject fp_name="/e_testbed/system/core/regs/r_regs[29]" type="array" db_ref_id="1">
30	35	<obj_property name="ElementShortName">[29]</obj_property>
31	36	<obj_property name="ObjectShortName">r_regs[29]</obj_property>

...	...	@@ -7,5 +7,23 @@
7	7	*/
8	8	unsigned int cyc_cnt_read(void);
9	9
	10	+/**
	11	+ * @brief delay for a number of cycles
	12	+ * @param[in] cyc number of cycles
	13	+ */
	14	+void cyc_cnt_delay(unsigned int cyc);
	15	+
	16	+/**
	17	+ * @brief delay for a number of microseconds
	18	+ * @param[in] us number of microseconds
	19	+ */
	20	+void cyc_cnt_delay_us(unsigned int us);
	21	+
	22	+/**
	23	+ * @brief delay for a number of milliseconds
	24	+ * @param[in] ms number of milliseconds
	25	+ */
	26	+void cyc_cnt_delay_ms(unsigned int ms);
	27	+
10	28	#endif /* #ifndef CYC_CNT_H */
11	29

...	...	@@ -1,13 +1,12 @@
1	1	#include "cyc_cnt.h"
	2	+#include "lcd.h"
2	3	#include "leds.h"
3	4
4	5	volatile int data[100];
5	6
6		-void delay()
	7	+void delay(void)
7	8	{
8		- unsigned int start = cyc_cnt_read();
9		- while (cyc_cnt_read() - start < 10000000)
10		- /* wait */;
	9	+ cyc_cnt_delay_ms(200);
11	10	}
12	11
13	12	int main()
...	...	@@ -17,6 +16,8 @@ int main()
17	16	for (i = 0; i < sizeof(data) / sizeof(data[0]); ++i)
18	17	data[i] = i;
19	18
	19	+ lcd_init();
	20	+
20	21	while (1) {
21	22	for (i = 0x1; i < 0x80; i <<= 1) {
22	23	leds_set_state(i);

...	...	@@ -28,8 +28,8 @@
28	28	<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
32		- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
	31	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
	32	+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
33	33	</file>
34	34	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35	35	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
...	...	@@ -52,26 +52,26 @@
52	52	<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
53	53	</file>
54	54	<file xil_pn:name="system/ram.vhd" xil_pn:type="FILE_VHDL">
55		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
56		- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
	55	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
	56	+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
57	57	</file>
58	58	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
59		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
60		- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
	59	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
	60	+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
61	61	</file>
62	62	<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
63		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
	63	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
64	64	<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
65	65	<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
66	66	<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
67	67	</file>
68	68	<file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
69		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
70		- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
	69	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
	70	+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
71	71	</file>
72	72	<file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
73		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
74		- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
	73	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
	74	+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
75	75	</file>
76	76	<file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
77	77	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...	...	@@ -83,8 +83,19 @@
83	83	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
84	84	</file>
85	85	<file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
86		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
87		- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
	86	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
	87	+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
	88	+ </file>
	89	+ <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
	90	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
	91	+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
	92	+ </file>
	93	+ <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
	94	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
	95	+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
	96	+ </file>
	97	+ <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
	98	+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
88	99	</file>
89	100	</files>
90	101
...	...	@@ -208,6 +219,7 @@
208	219	<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
209	220	<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
210	221	<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
	222	+ <property xil_pn:name="Last Selected UCF File" xil_pn:value="/home/stefan/spartan3/mips_sys/constraints/lcd.ucf" xil_pn:valueState="non-default"/>
211	223	<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
212	224	<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
213	225	<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
...	...	@@ -321,7 +333,7 @@
321	333	<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
322	334	<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
323	335	<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
324		- <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
	336	+ <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="100 us" xil_pn:valueState="non-default"/>
325	337	<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
326	338	<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
327	339	<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
...	...	@@ -400,6 +412,7 @@
400	412	<binding xil_pn:location="/e_system" xil_pn:name="constraints/leds.ucf"/>
401	413	<binding xil_pn:location="/e_system" xil_pn:name="constraints/clk.ucf"/>
402	414	<binding xil_pn:location="/e_system" xil_pn:name="constraints/rst.ucf"/>
	415	+ <binding xil_pn:location="/e_system" xil_pn:name="constraints/lcd.ucf"/>
403	416	</bindings>
404	417
405	418	<libraries/>

...	...	@@ -1,12 +1,14 @@
1	1	LIBRARY IEEE;
2	2	USE IEEE.STD_LOGIC_1164.ALL;
3	3	USE IEEE.NUMERIC_STD.ALL;
	4	+USE work.io_lcd_pins.all;
4	5
5	6	ENTITY e_system IS
6	7	PORT (
7	8	rst: IN std_logic;
8	9	clk: IN std_logic;
9		- pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
	10	+ pin_o_leds: OUT std_logic_vector(7 DOWNTO 0);
	11	+ pin_o_lcd: OUT t_io_lcd_pins
10	12	);
11	13	END ENTITY e_system;
12	14
...	...	@@ -25,6 +27,9 @@ ARCHITECTURE a_system OF e_system IS
25	27	SIGNAL s_leds_rd_data: std_logic_vector( 7 DOWNTO 0);
26	28	SIGNAL s_leds_wr_data: std_logic_vector( 7 DOWNTO 0);
27	29	SIGNAL s_leds_wr_en: std_logic;
	30	+ SIGNAL s_lcd_rd_data: std_logic_vector(31 DOWNTO 0);
	31	+ SIGNAL s_lcd_wr_data: std_logic_vector(31 DOWNTO 0);
	32	+ SIGNAL s_lcd_wr_en: std_logic_vector( 3 DOWNTO 0);
28	33	SIGNAL s_cyc_cnt_rd_data: std_logic_vector(31 DOWNTO 0);
29	34	SIGNAL s_cyc_cnt_wr_data: std_logic_vector(31 DOWNTO 0);
30	35	SIGNAL s_cyc_cnt_wr_en: std_logic;
...	...	@@ -79,6 +84,17 @@ ARCHITECTURE a_system OF e_system IS
79	84	);
80	85	END COMPONENT e_io_leds;
81	86
	87	+ COMPONENT e_io_lcd IS
	88	+ PORT (
	89	+ rst: IN std_logic;
	90	+ clk: IN std_logic;
	91	+ o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
	92	+ i_wr_data: IN std_logic_vector(31 DOWNTO 0);
	93	+ i_wr_en: IN std_logic_vector( 3 DOWNTO 0);
	94	+ pin_o_lcd: OUT t_io_lcd_pins
	95	+ );
	96	+ END COMPONENT e_io_lcd;
	97	+
82	98	COMPONENT e_io_cyc_cnt IS
83	99	PORT (
84	100	rst: IN std_logic;
...	...	@@ -117,6 +133,7 @@ BEGIN
117	133	p_dbus: PROCESS(s_dbus_addr, s_dbus_wr_data, s_dbus_wr_en,
118	134	s_data_rd_data,
119	135	s_leds_rd_data,
	136	+ s_lcd_rd_data,
120	137	s_cyc_cnt_rd_data)
121	138	VARIABLE v_wr_en_word: std_logic;
122	139	BEGIN
...	...	@@ -128,6 +145,10 @@ BEGIN
128	145	s_data_wr_en <= (OTHERS => '0');
129	146	s_leds_wr_data <= (OTHERS => '0');
130	147	s_leds_wr_en <= '0';
	148	+ s_lcd_wr_data <= (OTHERS => '0');
	149	+ s_lcd_wr_en <= (OTHERS => '0');
	150	+ s_cyc_cnt_wr_data <= (OTHERS => '0');
	151	+ s_cyc_cnt_wr_en <= '0';
131	152	IF s_dbus_addr(31) = '0' THEN
132	153	s_dbus_rd_data <= s_data_rd_data;
133	154	s_data_addr <= s_dbus_addr;
...	...	@@ -139,6 +160,10 @@ BEGIN
139	160	s_dbus_rd_data <= X"000000" & s_leds_rd_data;
140	161	s_leds_wr_data <= s_dbus_wr_data(7 DOWNTO 0);
141	162	s_leds_wr_en <= s_dbus_wr_en(0);
	163	+ WHEN X"01" =>
	164	+ s_dbus_rd_data <= s_lcd_rd_data;
	165	+ s_lcd_wr_data <= s_dbus_wr_data;
	166	+ s_lcd_wr_en <= s_dbus_wr_en;
142	167	WHEN X"10" =>
143	168	s_dbus_rd_data <= s_cyc_cnt_rd_data;
144	169	s_cyc_cnt_wr_data <= s_dbus_wr_data;
...	...	@@ -173,6 +198,16 @@ BEGIN
173	198	pin_o_leds => pin_o_leds
174	199	);
175	200
	201	+ lcd: e_io_lcd
	202	+ PORT MAP (
	203	+ rst => rst,
	204	+ clk => clk,
	205	+ o_rd_data => s_lcd_rd_data,
	206	+ i_wr_data => s_lcd_wr_data,
	207	+ i_wr_en => s_lcd_wr_en,
	208	+ pin_o_lcd => pin_o_lcd
	209	+ );
	210	+
176	211	cyc_cnt: e_io_cyc_cnt
177	212	PORT MAP (
178	213	rst => rst,

...	...	@@ -2,6 +2,7 @@ LIBRARY ieee;
2	2	USE ieee.std_logic_1164.all;
3	3	USE ieee.numeric_std.all;
4	4	USE std.textio.all;
	5	+USE work.io_lcd_pins.all;
5	6
6	7	ENTITY e_testbed IS
7	8	END ENTITY e_testbed;
...	...	@@ -12,13 +13,15 @@ ARCHITECTURE a_testbed OF e_testbed IS
12	13	PORT (
13	14	rst: IN std_logic;
14	15	clk: IN std_logic;
15		- pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
	16	+ pin_o_leds: OUT std_logic_vector(7 DOWNTO 0);
	17	+ pin_o_lcd: OUT t_io_lcd_pins
16	18	);
17	19	END COMPONENT e_system;
18	20
19	21	SIGNAL s_rst: std_logic;
20	22	SIGNAL s_clk: std_logic;
21	23	SIGNAL pin_leds: std_logic_vector(7 DOWNTO 0);
	24	+ SIGNAL pin_lcd: t_io_lcd_pins;
22	25
23	26	BEGIN
24	27
...	...	@@ -26,7 +29,8 @@ BEGIN
26	29	PORT MAP (
27	30	clk => s_clk,
28	31	rst => s_rst,
29		- pin_o_leds => pin_leds
	32	+ pin_o_leds => pin_leds,
	33	+ pin_o_lcd => pin_lcd
30	34	);
31	35
32	36	p_rst_clk: PROCESS
33	37