added "LEDs" I/O peripheral changed instruction memory from dpram to generated rom improved firmware structure to generate rom VHDL code (420617e) - mips_sys · BlinkenArea

added "LEDs" I/O peripheral changed instruction memory from dpram to generated rom improved firmware structure to generate rom VHDL code

Parent ae745be

Stefan Schuermans commited on 2012-02-10 22:43:28
Showing 14 changed files, with 234 additions and 142 deletions.

fw/.gitignore 81813a0..72ba3b1
fw/Makefile 1376684..86e2e49
fw/boot.s c391991..8576c9a
fw/leds.c 0000000..d41a027
fw/leds.h 0000000..373e669
fw/lnk.cmd c742987..c6b4d41
fw/main.c 9aa81cb..e7da1a6
fw/rom.head.vhd 0000000..44b0396
fw/rom.tail.vhd 0000000..65dc39f
io/leds.vhd 0000000..4ba3309
mips_sys.xise 1aadacb..219a92c
system/dpram.vhd c0882a8..0000000
system/system.vhd 353328b..2dffa21
test/testbed.vhd 6107532..5f56322

fw/.gitignore

View file @ 420617e

...	...	@@ -1,4 +1,6 @@
	1	+*.d
1	2	*.o
	3	+deps
2	4	fw
3	5	fw.bin
4		-fw.dat
	6	+rom.vhd

fw/Makefile

View file @ 420617e

@@ -1,31 +1,52 @@
+SRCS=main.c leds.c
+
 CC=mipsel-elf-gcc
 LD=mipsel-elf-ld
 OBJCOPY=mipsel-elf-objcopy
-CFLAGS=-Wall -Wextra
-LFLAGS=
+CFLAGS=-Wall -Wextra -mips1 -mno-abicalls
+LFLAGS=-mips1
+
+BASES=$(patsubst %.c,%,$(SRCS))
+DEPS=$(addsuffix .d,$(BASES))
+OBJS=$(addsuffix .o,$(BASES))
+
+.PHONY: all clean
+
+all: rom.vhd
+
+ifneq ($(MAKECMDGOALS),clean)
+  include deps
+endif
 
-.phony: all clean
+deps: $(DEPS)
+	cat /dev/null $^ >$@
 
-all: fw.dat
+%.d: %.c Makefile
+	$(CC) $(CFLAGS) -M -o $@ $<
 
-%.o: %.c
+%.o: %.c Makefile
 	$(CC) $(CFLAGS) -c -o $@ $<
 
-%.o: %.s
+%.o: %.s Makefile
 	$(CC) $(CFLAGS) -c -o $@ $<
 
-fw.o: main.o
+fw.o: $(OBJS)
 	$(LD) $(LFLAGS) -r -o $@ $^
 
 fw: lnk.cmd boot.o fw.o
 	$(LD) $(LFLAGS) -T lnk.cmd -o $@ boot.o fw.o
 
 fw.bin: fw
-	$(OBJCOPY) -O binary $< $@
+	$(OBJCOPY) -j .text -O binary $< $@
 
-fw.dat: fw.bin
-	hexdump -e '2/2 "%u " "\n"' -v $< >$@
+rom.vhd: rom.head.vhd rom.tail.vhd fw.bin
+	cat rom.head.vhd >$@
+	hexdump -e '1/4 "%08X\n"' -v fw.bin | \
+	  sed 's/^/=> X"/;s/$$/",/' | \
+	  nl -p -v 0 | \
+	  sed 's/^/        /' >>$@
+	cat rom.tail.vhd >>$@
 
 clean:
-	rm -f *.o fw fw.bin fw.dat
+	rm -f $(OBJS) boot.o fw.o fw fw.bin rom.vhd
 

fw/boot.s

View file @ 420617e

...	...	@@ -1,2 +1,6 @@
	1	+_begin:
1	2	lui $sp,0x0002
2	3	ori $sp,0x0000
	4	+ jal main
	5	+_end:
	6	+ j _end

fw/leds.c

View file @ 420617e

...	...	@@ -0,0 +1,12 @@
	1	+#include "leds.h"
	2	+
	3	+/**
	4	+ * @brief set state of LEDS
	5	+ * @param[in] state LED state
	6	+ */
	7	+void leds_set_state(unsigned char state)
	8	+{
	9	+ volatile unsigned char p_leds = (volatile unsigned char )0x80000000;
	10	+ *p_leds = state;
	11	+}
	12	+

fw/leds.h

View file @ 420617e

...	...	@@ -0,0 +1,11 @@
	1	+#ifndef LEDS_H
	2	+#define LEDS_H
	3	+
	4	+/**
	5	+ * @brief set state of LEDS
	6	+ * @param[in] state LED state
	7	+ */
	8	+void leds_set_state(unsigned char state);
	9	+
	10	+#endif /* #ifndef LEDS_H */
	11	+

fw/lnk.cmd

View file @ 420617e

@@ -2,7 +2,7 @@ SECTIONS
 {
   . = 0x00000000;
   .text : { *(.text) }
-  . = 0x00000800;
+  . = 0x00001000;
   .data : { *(.data) }
   .bss : { *(.bss) }
 }

fw/main.c

View file @ 420617e

@@ -1,12 +1,17 @@
-int global = 1;
+#include "leds.h"
+
+int data[10];
 
 int main()
 {
-  volatile int *data = (volatile int *)0x00;
-  int i;
-  for (i = 0; i < 10; ++i)
+  unsigned int i;
+
+  for (i = 0; i < sizeof(data) / sizeof(data[0]); ++i)
     data[i] = i;
 
+  for (i = 0x1; i < 0x100; i <<= 1)
+    leds_set_state(i);
+
   return 0;
 }
 

fw/rom.head.vhd

View file @ 420617e

...	...	@@ -0,0 +1,22 @@
	1	+LIBRARY IEEE;
	2	+USE IEEE.STD_LOGIC_1164.ALL;
	3	+USE IEEE.NUMERIC_STD.ALL;
	4	+
	5	+ENTITY e_rom IS
	6	+ GENERIC (
	7	+ addr_width: INTEGER
	8	+ );
	9	+ PORT (
	10	+ clk: IN std_logic;
	11	+ i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	12	+ o_data: OUT std_logic_vector( 31 DOWNTO 0)
	13	+ );
	14	+END ENTITY e_rom;
	15	+
	16	+ARCHITECTURE a_rom OF e_rom IS
	17	+
	18	+ SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
	19	+ SUBTYPE t_data IS std_logic_vector( 31 DOWNTO 0);
	20	+ TYPE t_buf IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
	21	+
	22	+ SIGNAL s_buf: t_buf := (

fw/rom.tail.vhd

View file @ 420617e

...	...	@@ -0,0 +1,14 @@
	1	+ OTHERS => X"00000000"
	2	+ );
	3	+
	4	+BEGIN
	5	+
	6	+ p_rom: PROCESS(clk)
	7	+ BEGIN
	8	+ IF rising_edge(clk) THEN
	9	+ o_data <= s_buf(to_integer(unsigned(i_addr)));
	10	+ END IF;
	11	+ END PROCESS p_rom;
	12	+
	13	+END ARCHITECTURE a_rom;
	14	+

io/leds.vhd

View file @ 420617e

...	...	@@ -0,0 +1,46 @@
	1	+LIBRARY IEEE;
	2	+USE IEEE.STD_LOGIC_1164.ALL;
	3	+USE IEEE.NUMERIC_STD.ALL;
	4	+
	5	+ENTITY e_io_leds IS
	6	+ PORT (
	7	+ rst: IN std_logic;
	8	+ clk: IN std_logic;
	9	+ o_rd_data: OUT std_logic_vector(7 DOWNTO 0);
	10	+ i_wr_data: IN std_logic_vector(7 DOWNTO 0);
	11	+ i_wr_en: IN std_logic;
	12	+ pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
	13	+ );
	14	+END ENTITY e_io_leds;
	15	+
	16	+ARCHITECTURE a_io_leds OF e_io_leds IS
	17	+
	18	+ SIGNAL n_leds: std_logic_vector(7 DOWNTO 0);
	19	+ SIGNAL r_leds: std_logic_vector(7 DOWNTO 0);
	20	+
	21	+BEGIN
	22	+
	23	+ o_rd_data <= r_leds;
	24	+
	25	+ p_write: PROCESS(r_leds, i_wr_data, i_wr_en)
	26	+ BEGIN
	27	+ IF i_wr_en = '1' THEN
	28	+ n_leds <= i_wr_data;
	29	+ ELSE
	30	+ n_leds <= r_leds;
	31	+ END IF;
	32	+ END PROCESS p_write;
	33	+
	34	+ pin_o_leds <= r_leds;
	35	+
	36	+ p_sync: PROCESS(rst, clk)
	37	+ BEGIN
	38	+ IF rst = '1' THEN
	39	+ r_leds <= (OTHERS => '0');
	40	+ ELSIF rising_edge(clk) THEN
	41	+ r_leds <= n_leds;
	42	+ END IF;
	43	+ END PROCESS p_sync;
	44	+
	45	+END ARCHITECTURE a_io_leds;
	46	+

mips_sys.xise

View file @ 420617e

@@ -28,7 +28,7 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
@@ -62,19 +62,23 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
-    <file xil_pn:name="system/dpram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
-    </file>
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
     </file>
+    <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
+    </file>
+    <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
+    </file>
   </files>
 
   <properties>

system/dpram.vhd

View file @ ae745be

@@ -1,41 +0,0 @@
                         -LIBRARY IEEE;
                         -USE IEEE.STD_LOGIC_1164.ALL;
                         -USE IEEE.NUMERIC_STD.ALL;
+                        -
                         -ENTITY e_dpram IS
                         -    GENERIC (
                         -        addr_width: natural;
                         -        data_width: natural
                         -    );
                         -    PORT (
                         -        clk:       IN  std_logic;
                         -        i_rd_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
                         -        o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
                         -        i_wr_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
                         -        i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
                         -        i_wr_en:   IN  std_logic
                         -    );
                         -END ENTITY e_dpram;
+                        -
                         -ARCHITECTURE a_dpram OF e_dpram IS
+                        -
                         -    SUBTYPE t_addr IS std_logic_vector(addr_width - 1 DOWNTO 0);
                         -    SUBTYPE t_data IS std_logic_vector(data_width - 1 DOWNTO 0);
                         -    TYPE    t_buf  IS ARRAY(0 TO 2 ** addr_width - 1) OF t_data;
+                        -
                         -    SIGNAL s_buf: t_buf;
+                        -
                         -BEGIN
+                        -
                         -    p_dpram: PROCESS(clk)
                         -    BEGIN
                         -        IF rising_edge(clk) THEN
                         -            IF i_wr_en = '1' THEN
                         -                s_buf(to_integer(unsigned(i_wr_addr))) <= i_wr_data;
                         -            END IF;
                         -            o_rd_data <= s_buf(to_integer(unsigned(i_rd_addr)));
                         -        END IF;
                         -    END PROCESS p_dpram;
+                        -
                         -END ARCHITECTURE a_dpram;
+                        -

system/system.vhd

View file @ 420617e

@@ -6,11 +6,7 @@ ENTITY e_system IS
     PORT (
         rst:          IN  std_logic;
         clk:          IN  std_logic;
-        i_core_stall: IN  std_logic;
-        i_prg_addr:   IN  std_logic_vector(31 DOWNTO 0);
-        i_prg_data:   IN  std_logic_vector(31 DOWNTO 0);
-        i_prg_en:     IN  std_logic;
-        o_dummy:      OUT std_logic_vector(31 DOWNTO 0)
+        pin_o_leds:   OUT std_logic_vector(7 DOWNTO 0)
     );
 END ENTITY e_system;
 
@@ -18,10 +14,17 @@ ARCHITECTURE a_system OF e_system IS
 
     SIGNAL s_instr_addr:   std_logic_vector(31 DOWNTO 0);
     SIGNAL s_instr_data:   std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_dbus_addr:    std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_dbus_rd_data: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_dbus_wr_data: std_logic_vector(31 DOWNTO 0);
+    SIGNAL s_dbus_wr_en:   std_logic_vector( 3 DOWNTO 0);
     SIGNAL s_data_addr:    std_logic_vector(31 DOWNTO 0);
     SIGNAL s_data_rd_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_data_wr_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_data_wr_en:   std_logic_vector( 3 DOWNTO 0);
+    SIGNAL s_leds_rd_data: std_logic_vector( 7 DOWNTO 0);
+    SIGNAL s_leds_wr_data: std_logic_vector( 7 DOWNTO 0);
+    SIGNAL s_leds_wr_en:   std_logic;
 
     COMPONENT e_mips_core IS
         PORT (
@@ -37,34 +40,41 @@ ARCHITECTURE a_system OF e_system IS
         );
     END COMPONENT e_mips_core;
 
-    COMPONENT e_ram IS
+    COMPONENT e_rom IS
         GENERIC (
-            addr_width: natural;
-            data_width: natural
+            addr_width: INTEGER
         );
         PORT (
             clk:    IN  std_logic;
             i_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
-            o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
-            i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
-            i_wr_en:   IN  std_logic
+            o_data: OUT std_logic_vector(            31 DOWNTO 0)
         );
-    END COMPONENT e_ram;
+    END COMPONENT e_rom;
 
-    COMPONENT e_dpram IS
+    COMPONENT e_ram IS
         GENERIC (
             addr_width: natural;
             data_width: natural
         );
         PORT (
             clk:       IN  std_logic;
-            i_rd_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
+            i_addr:    IN  std_logic_vector(addr_width - 1 DOWNTO 0);
             o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
-            i_wr_addr: IN  std_logic_vector(addr_width - 1 DOWNTO 0);
             i_wr_data: IN  std_logic_vector(data_width - 1 DOWNTO 0);
             i_wr_en:   IN  std_logic
         );
-    END COMPONENT e_dpram;
+    END COMPONENT e_ram;
+
+    COMPONENT e_io_leds IS
+        PORT (
+            rst:        IN  std_logic;
+            clk:        IN  std_logic;
+            o_rd_data:  OUT std_logic_vector(7 DOWNTO 0);
+            i_wr_data:  IN  std_logic_vector(7 DOWNTO 0);
+            i_wr_en:    IN  std_logic;
+            pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
+        );
+    END COMPONENT e_io_leds;
 
 BEGIN
 
@@ -72,29 +82,47 @@ BEGIN
         PORT MAP (
             rst            => rst,
             clk            => clk,
-            i_stall        => i_core_stall,
+            i_stall        => '0',
             o_instr_addr   => s_instr_addr,
             i_instr_data   => s_instr_data,
-            o_data_addr    => s_data_addr,
-            i_data_rd_data => s_data_rd_data,
-            o_data_wr_data => s_data_wr_data,
-            o_data_wr_en   => s_data_wr_en
+            o_data_addr    => s_dbus_addr,
+            i_data_rd_data => s_dbus_rd_data,
+            o_data_wr_data => s_dbus_wr_data,
+            o_data_wr_en   => s_dbus_wr_en
         );
 
-    instr: e_dpram
+    instr: e_rom
         GENERIC MAP (
-            addr_width => 10,
-            data_width => 32
+            addr_width => 10
         )
         PORT MAP (
             clk    => clk,
-            i_rd_addr => s_instr_addr(11 DOWNTO 2),
-            o_rd_data => s_instr_data,
-            i_wr_addr => i_prg_addr(11 DOWNTO 2),
-            i_wr_data => i_prg_data,
-            i_wr_en   => i_prg_en
+            i_addr => s_instr_addr(11 DOWNTO 2),
+            o_data => s_instr_data
         );
 
+    p_dbus: PROCESS(s_dbus_addr, s_dbus_wr_data, s_dbus_wr_en,
+                    s_data_rd_data,
+                    s_leds_rd_data)
+    BEGIN
+        s_dbus_rd_data <= (OTHERS => '0');
+        s_data_addr    <= (OTHERS => '0');
+        s_data_wr_data <= (OTHERS => '0');
+        s_data_wr_en   <= (OTHERS => '0');
+        s_leds_wr_data <= (OTHERS => '0');
+        s_leds_wr_en   <= '0';
+        IF s_dbus_addr(31) = '0' THEN
+            s_dbus_rd_data <= s_data_rd_data;
+            s_data_addr    <= s_dbus_addr;
+            s_data_wr_data <= s_dbus_wr_data;
+            s_data_wr_en   <= s_dbus_wr_en;
+        ELSIF s_dbus_addr(31 DOWNTO 0) = X"80000000" THEN
+            s_dbus_rd_data <= X"000000" & s_leds_rd_data;
+            s_leds_wr_data <= s_dbus_wr_data(7 DOWNTO 0);
+            s_leds_wr_en   <= s_dbus_wr_en(0);
+        END IF;
+    END PROCESS p_dbus;
+
     data: FOR i IN 0 TO 3 GENERATE
         databank: e_ram
             GENERIC MAP (
@@ -110,6 +138,14 @@ BEGIN
             );
     END GENERATE data;
 
-    o_dummy <= s_data_wr_data;
+    leds: e_io_leds
+        PORT MAP (
+            rst        => rst,
+            clk        => clk,
+            o_rd_data  => s_leds_rd_data,
+            i_wr_data  => s_leds_wr_data,
+            i_wr_en    => s_leds_wr_en,
+            pin_o_leds => pin_o_leds
+        );
 
 END ARCHITECTURE a_system;

test/testbed.vhd

View file @ 420617e

@@ -12,21 +12,13 @@ ARCHITECTURE a_testbed OF e_testbed IS
         PORT (
             rst:          IN  std_logic;
             clk:          IN  std_logic;
-            i_core_stall: IN  std_logic;
-            i_prg_addr:   IN  std_logic_vector(31 DOWNTO 0);
-            i_prg_data:   IN  std_logic_vector(31 DOWNTO 0);
-            i_prg_en:     IN  std_logic;
-            o_dummy:      OUT std_logic_vector(31 DOWNTO 0)
+            pin_o_leds:   OUT std_logic_vector(7 DOWNTO 0)
         );
     END COMPONENT e_system;
 
     SIGNAL s_rst:    std_logic;
     SIGNAL s_clk:    std_logic;
-    SIGNAL s_core_stall: std_logic;
-    SIGNAL s_prg_addr:   std_logic_vector(31 DOWNTO 0);
-    SIGNAL s_prg_data:   std_logic_vector(31 DOWNTO 0);
-    SIGNAL s_prg_en:     std_logic;
-    SIGNAL s_dummy:      std_logic_vector(31 DOWNTO 0);
+    SIGNAL pin_leds: std_logic_vector(7 DOWNTO 0);
 
 BEGIN
 
@@ -34,55 +26,19 @@ BEGIN
         PORT MAP (
             clk        => s_clk,
             rst        => s_rst,
-            i_core_stall => s_core_stall,
-            i_prg_addr   => s_prg_addr,
-            i_prg_data   => s_prg_data,
-            i_prg_en     => s_prg_en,
-            o_dummy      => s_dummy
+            pin_o_leds => pin_leds
         );
 
     p_rst_clk: PROCESS
-        FILE     f_data:  text IS "fw/fw.dat";
-        VARIABLE v_line:  line;
-        VARIABLE v_addr:  integer;
-        VARIABLE v_data1: integer;
-        VARIABLE v_data2: integer;
     BEGIN
         s_rst        <= '0';
         s_clk        <= '0';
-        s_core_stall <= '1';
-        s_prg_addr   <= (OTHERS => '0');
-        s_prg_data   <= (OTHERS => '0');
-        s_prg_en     <= '0';
-
-        WAIT FOR 1 ps;
-        s_rst <= '1';
-        WAIT FOR 1 ps;
-        s_rst <= '0';
-
-        s_prg_en <= '1';
-        v_addr   := 0;
-        WHILE NOT endfile(f_data) LOOP
-            readline(f_data, v_line);
-            read(v_line, v_data1);
-            read(v_line, v_data2);
-            s_prg_addr <= std_logic_vector(to_unsigned(v_addr, 32));
-            s_prg_data <= std_logic_vector(to_unsigned(v_data2, 16)) &
-                          std_logic_vector(to_unsigned(v_data1, 16));
-            WAIT FOR 1 ps;
-            s_clk <= '1';
-            WAIT FOR 1 ps;
-            s_clk <= '0';
-            v_addr := v_addr + 4;
-        END LOOP;
-        s_prg_en <= '0';
 
         WAIT FOR 10 ns;
         s_rst <= '1';
         WAIT FOR 10 ns;
         s_rst <= '0';
 
-        s_core_stall <= '0';
         WHILE TRUE LOOP
             WAIT FOR 10 ns;
             s_clk <= '1';


...	...	@@ -1,31 +1,52 @@
	1	+SRCS=main.c leds.c
	2	+
1	3	CC=mipsel-elf-gcc
2	4	LD=mipsel-elf-ld
3	5	OBJCOPY=mipsel-elf-objcopy
4		-CFLAGS=-Wall -Wextra
5		-LFLAGS=
	6	+CFLAGS=-Wall -Wextra -mips1 -mno-abicalls
	7	+LFLAGS=-mips1
	8	+
	9	+BASES=$(patsubst %.c,%,$(SRCS))
	10	+DEPS=$(addsuffix .d,$(BASES))
	11	+OBJS=$(addsuffix .o,$(BASES))
	12	+
	13	+.PHONY: all clean
	14	+
	15	+all: rom.vhd
	16	+
	17	+ifneq ($(MAKECMDGOALS),clean)
	18	+ include deps
	19	+endif
6	20
7		-.phony: all clean
	21	+deps: $(DEPS)
	22	+ cat /dev/null $^ >$@
8	23
9		-all: fw.dat
	24	+%.d: %.c Makefile
	25	+ $(CC) $(CFLAGS) -M -o $@ $<
10	26
11		-%.o: %.c
	27	+%.o: %.c Makefile
12	28	$(CC) $(CFLAGS) -c -o $@ $<
13	29
14		-%.o: %.s
	30	+%.o: %.s Makefile
15	31	$(CC) $(CFLAGS) -c -o $@ $<
16	32
17		-fw.o: main.o
	33	+fw.o: $(OBJS)
18	34	$(LD) $(LFLAGS) -r -o $@ $^
19	35
20	36	fw: lnk.cmd boot.o fw.o
21	37	$(LD) $(LFLAGS) -T lnk.cmd -o $@ boot.o fw.o
22	38
23	39	fw.bin: fw
24		- $(OBJCOPY) -O binary $< $@
	40	+ $(OBJCOPY) -j .text -O binary $< $@
25	41
26		-fw.dat: fw.bin
27		- hexdump -e '2/2 "%u " "\n"' -v $< >$@
	42	+rom.vhd: rom.head.vhd rom.tail.vhd fw.bin
	43	+ cat rom.head.vhd >$@
	44	+ hexdump -e '1/4 "%08X\n"' -v fw.bin \| \
	45	+ sed 's/^/=> X"/;s/$$/",/' \| \
	46	+ nl -p -v 0 \| \
	47	+ sed 's/^/ /' >>$@
	48	+ cat rom.tail.vhd >>$@
28	49
29	50	clean:
30		- rm -f *.o fw fw.bin fw.dat
	51	+ rm -f $(OBJS) boot.o fw.o fw fw.bin rom.vhd
31	52

...	...	@@ -2,7 +2,7 @@ SECTIONS
2	2	{
3	3	. = 0x00000000;
4	4	.text : { *(.text) }
5		- . = 0x00000800;
	5	+ . = 0x00001000;
6	6	.data : { *(.data) }
7	7	.bss : { *(.bss) }
8	8	}

...	...	@@ -1,12 +1,17 @@
1		-int global = 1;
	1	+#include "leds.h"
	2	+
	3	+int data[10];
2	4
3	5	int main()
4	6	{
5		- volatile int data = (volatile int )0x00;
6		- int i;
7		- for (i = 0; i < 10; ++i)
	7	+ unsigned int i;
	8	+
	9	+ for (i = 0; i < sizeof(data) / sizeof(data[0]); ++i)
8	10	data[i] = i;
9	11
	12	+ for (i = 0x1; i < 0x100; i <<= 1)
	13	+ leds_set_state(i);
	14	+
10	15	return 0;
11	16	}
12	17

...	...	@@ -28,7 +28,7 @@
28	28	<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
	31	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
32	32	<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
33	33	</file>
34	34	<file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
...	...	@@ -62,19 +62,23 @@
62	62	<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
63	63	</file>
64	64	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
65		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
	65	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
66	66	<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
67	67	</file>
68		- <file xil_pn:name="system/dpram.vhd" xil_pn:type="FILE_VHDL">
69		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
70		- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
71		- </file>
72	68	<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
73		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
	69	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
74	70	<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
75	71	<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
76	72	<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
77	73	</file>
	74	+ <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
	75	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
	76	+ <association xil_pn:name="Implementation" xil_pn:seqID="140"/>
	77	+ </file>
	78	+ <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
	79	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
	80	+ <association xil_pn:name="Implementation" xil_pn:seqID="141"/>
	81	+ </file>
78	82	</files>
79	83
80	84	<properties>

...	...	@@ -6,11 +6,7 @@ ENTITY e_system IS
6	6	PORT (
7	7	rst: IN std_logic;
8	8	clk: IN std_logic;
9		- i_core_stall: IN std_logic;
10		- i_prg_addr: IN std_logic_vector(31 DOWNTO 0);
11		- i_prg_data: IN std_logic_vector(31 DOWNTO 0);
12		- i_prg_en: IN std_logic;
13		- o_dummy: OUT std_logic_vector(31 DOWNTO 0)
	9	+ pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
14	10	);
15	11	END ENTITY e_system;
16	12
...	...	@@ -18,10 +14,17 @@ ARCHITECTURE a_system OF e_system IS
18	14
19	15	SIGNAL s_instr_addr: std_logic_vector(31 DOWNTO 0);
20	16	SIGNAL s_instr_data: std_logic_vector(31 DOWNTO 0);
	17	+ SIGNAL s_dbus_addr: std_logic_vector(31 DOWNTO 0);
	18	+ SIGNAL s_dbus_rd_data: std_logic_vector(31 DOWNTO 0);
	19	+ SIGNAL s_dbus_wr_data: std_logic_vector(31 DOWNTO 0);
	20	+ SIGNAL s_dbus_wr_en: std_logic_vector( 3 DOWNTO 0);
21	21	SIGNAL s_data_addr: std_logic_vector(31 DOWNTO 0);
22	22	SIGNAL s_data_rd_data: std_logic_vector(31 DOWNTO 0);
23	23	SIGNAL s_data_wr_data: std_logic_vector(31 DOWNTO 0);
24	24	SIGNAL s_data_wr_en: std_logic_vector( 3 DOWNTO 0);
	25	+ SIGNAL s_leds_rd_data: std_logic_vector( 7 DOWNTO 0);
	26	+ SIGNAL s_leds_wr_data: std_logic_vector( 7 DOWNTO 0);
	27	+ SIGNAL s_leds_wr_en: std_logic;
25	28
26	29	COMPONENT e_mips_core IS
27	30	PORT (
...	...	@@ -37,34 +40,41 @@ ARCHITECTURE a_system OF e_system IS
37	40	);
38	41	END COMPONENT e_mips_core;
39	42
40		- COMPONENT e_ram IS
	43	+ COMPONENT e_rom IS
41	44	GENERIC (
42		- addr_width: natural;
43		- data_width: natural
	45	+ addr_width: INTEGER
44	46	);
45	47	PORT (
46	48	clk: IN std_logic;
47	49	i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
48		- o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
49		- i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
50		- i_wr_en: IN std_logic
	50	+ o_data: OUT std_logic_vector( 31 DOWNTO 0)
51	51	);
52		- END COMPONENT e_ram;
	52	+ END COMPONENT e_rom;
53	53
54		- COMPONENT e_dpram IS
	54	+ COMPONENT e_ram IS
55	55	GENERIC (
56	56	addr_width: natural;
57	57	data_width: natural
58	58	);
59	59	PORT (
60	60	clk: IN std_logic;
61		- i_rd_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
	61	+ i_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
62	62	o_rd_data: OUT std_logic_vector(data_width - 1 DOWNTO 0);
63		- i_wr_addr: IN std_logic_vector(addr_width - 1 DOWNTO 0);
64	63	i_wr_data: IN std_logic_vector(data_width - 1 DOWNTO 0);
65	64	i_wr_en: IN std_logic
66	65	);
67		- END COMPONENT e_dpram;
	66	+ END COMPONENT e_ram;
	67	+
	68	+ COMPONENT e_io_leds IS
	69	+ PORT (
	70	+ rst: IN std_logic;
	71	+ clk: IN std_logic;
	72	+ o_rd_data: OUT std_logic_vector(7 DOWNTO 0);
	73	+ i_wr_data: IN std_logic_vector(7 DOWNTO 0);
	74	+ i_wr_en: IN std_logic;
	75	+ pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
	76	+ );
	77	+ END COMPONENT e_io_leds;
68	78
69	79	BEGIN
70	80
...	...	@@ -72,29 +82,47 @@ BEGIN
72	82	PORT MAP (
73	83	rst => rst,
74	84	clk => clk,
75		- i_stall => i_core_stall,
	85	+ i_stall => '0',
76	86	o_instr_addr => s_instr_addr,
77	87	i_instr_data => s_instr_data,
78		- o_data_addr => s_data_addr,
79		- i_data_rd_data => s_data_rd_data,
80		- o_data_wr_data => s_data_wr_data,
81		- o_data_wr_en => s_data_wr_en
	88	+ o_data_addr => s_dbus_addr,
	89	+ i_data_rd_data => s_dbus_rd_data,
	90	+ o_data_wr_data => s_dbus_wr_data,
	91	+ o_data_wr_en => s_dbus_wr_en
82	92	);
83	93
84		- instr: e_dpram
	94	+ instr: e_rom
85	95	GENERIC MAP (
86		- addr_width => 10,
87		- data_width => 32
	96	+ addr_width => 10
88	97	)
89	98	PORT MAP (
90	99	clk => clk,
91		- i_rd_addr => s_instr_addr(11 DOWNTO 2),
92		- o_rd_data => s_instr_data,
93		- i_wr_addr => i_prg_addr(11 DOWNTO 2),
94		- i_wr_data => i_prg_data,
95		- i_wr_en => i_prg_en
	100	+ i_addr => s_instr_addr(11 DOWNTO 2),
	101	+ o_data => s_instr_data
96	102	);
97	103
	104	+ p_dbus: PROCESS(s_dbus_addr, s_dbus_wr_data, s_dbus_wr_en,
	105	+ s_data_rd_data,
	106	+ s_leds_rd_data)
	107	+ BEGIN
	108	+ s_dbus_rd_data <= (OTHERS => '0');
	109	+ s_data_addr <= (OTHERS => '0');
	110	+ s_data_wr_data <= (OTHERS => '0');
	111	+ s_data_wr_en <= (OTHERS => '0');
	112	+ s_leds_wr_data <= (OTHERS => '0');
	113	+ s_leds_wr_en <= '0';
	114	+ IF s_dbus_addr(31) = '0' THEN
	115	+ s_dbus_rd_data <= s_data_rd_data;
	116	+ s_data_addr <= s_dbus_addr;
	117	+ s_data_wr_data <= s_dbus_wr_data;
	118	+ s_data_wr_en <= s_dbus_wr_en;
	119	+ ELSIF s_dbus_addr(31 DOWNTO 0) = X"80000000" THEN
	120	+ s_dbus_rd_data <= X"000000" & s_leds_rd_data;
	121	+ s_leds_wr_data <= s_dbus_wr_data(7 DOWNTO 0);
	122	+ s_leds_wr_en <= s_dbus_wr_en(0);
	123	+ END IF;
	124	+ END PROCESS p_dbus;
	125	+
98	126	data: FOR i IN 0 TO 3 GENERATE
99	127	databank: e_ram
100	128	GENERIC MAP (
...	...	@@ -110,6 +138,14 @@ BEGIN
110	138	);
111	139	END GENERATE data;
112	140
113		- o_dummy <= s_data_wr_data;
	141	+ leds: e_io_leds
	142	+ PORT MAP (
	143	+ rst => rst,
	144	+ clk => clk,
	145	+ o_rd_data => s_leds_rd_data,
	146	+ i_wr_data => s_leds_wr_data,
	147	+ i_wr_en => s_leds_wr_en,
	148	+ pin_o_leds => pin_o_leds
	149	+ );
114	150
115	151	END ARCHITECTURE a_system;

...	...	@@ -12,21 +12,13 @@ ARCHITECTURE a_testbed OF e_testbed IS
12	12	PORT (
13	13	rst: IN std_logic;
14	14	clk: IN std_logic;
15		- i_core_stall: IN std_logic;
16		- i_prg_addr: IN std_logic_vector(31 DOWNTO 0);
17		- i_prg_data: IN std_logic_vector(31 DOWNTO 0);
18		- i_prg_en: IN std_logic;
19		- o_dummy: OUT std_logic_vector(31 DOWNTO 0)
	15	+ pin_o_leds: OUT std_logic_vector(7 DOWNTO 0)
20	16	);
21	17	END COMPONENT e_system;
22	18
23	19	SIGNAL s_rst: std_logic;
24	20	SIGNAL s_clk: std_logic;
25		- SIGNAL s_core_stall: std_logic;
26		- SIGNAL s_prg_addr: std_logic_vector(31 DOWNTO 0);
27		- SIGNAL s_prg_data: std_logic_vector(31 DOWNTO 0);
28		- SIGNAL s_prg_en: std_logic;
29		- SIGNAL s_dummy: std_logic_vector(31 DOWNTO 0);
	21	+ SIGNAL pin_leds: std_logic_vector(7 DOWNTO 0);
30	22
31	23	BEGIN
32	24
...	...	@@ -34,55 +26,19 @@ BEGIN
34	26	PORT MAP (
35	27	clk => s_clk,
36	28	rst => s_rst,
37		- i_core_stall => s_core_stall,
38		- i_prg_addr => s_prg_addr,
39		- i_prg_data => s_prg_data,
40		- i_prg_en => s_prg_en,
41		- o_dummy => s_dummy
	29	+ pin_o_leds => pin_leds
42	30	);
43	31
44	32	p_rst_clk: PROCESS
45		- FILE f_data: text IS "fw/fw.dat";
46		- VARIABLE v_line: line;
47		- VARIABLE v_addr: integer;
48		- VARIABLE v_data1: integer;
49		- VARIABLE v_data2: integer;
50	33	BEGIN
51	34	s_rst <= '0';
52	35	s_clk <= '0';
53		- s_core_stall <= '1';
54		- s_prg_addr <= (OTHERS => '0');
55		- s_prg_data <= (OTHERS => '0');
56		- s_prg_en <= '0';
57		-
58		- WAIT FOR 1 ps;
59		- s_rst <= '1';
60		- WAIT FOR 1 ps;
61		- s_rst <= '0';
62		-
63		- s_prg_en <= '1';
64		- v_addr := 0;
65		- WHILE NOT endfile(f_data) LOOP
66		- readline(f_data, v_line);
67		- read(v_line, v_data1);
68		- read(v_line, v_data2);
69		- s_prg_addr <= std_logic_vector(to_unsigned(v_addr, 32));
70		- s_prg_data <= std_logic_vector(to_unsigned(v_data2, 16)) &
71		- std_logic_vector(to_unsigned(v_data1, 16));
72		- WAIT FOR 1 ps;
73		- s_clk <= '1';
74		- WAIT FOR 1 ps;
75		- s_clk <= '0';
76		- v_addr := v_addr + 4;
77		- END LOOP;
78		- s_prg_en <= '0';
79	36
80	37	WAIT FOR 10 ns;
81	38	s_rst <= '1';
82	39	WAIT FOR 10 ns;
83	40	s_rst <= '0';
84	41
85		- s_core_stall <= '0';
86	42	WHILE TRUE LOOP
87	43	WAIT FOR 10 ns;
88	44	s_clk <= '1';
89	45