adapt ethernet TX clock timing constraint to transmission of data on falling edge
Stefan Schuermans commited on 2012-03-07 21:18:54
Showing 1 changed files, with 1 additions and 1 deletions.
- constraints/eth.ucf fa87c85..8f5374e
| ... | ... |
@@ -15,4 +15,4 @@ NET "pin_o_eth_txd[2]" LOC = "E6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE |
| 15 | 15 |
NET "pin_o_eth_txd[3]" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 4; |
| 16 | 16 |
NET "pin_o_eth_tx_en" LOC = "D8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 4; |
| 17 | 17 |
TIMESPEC TS_pin_i_eth_rx_clk = PERIOD "pin_i_eth_rx_clk" 40 ns HIGH 50%; |
| 18 |
-TIMESPEC TS_pin_i_eth_tx_clk = PERIOD "pin_i_eth_tx_clk" 40 ns HIGH 50%; |
|
| 18 |
+TIMESPEC TS_pin_i_eth_tx_clk = PERIOD "pin_i_eth_tx_clk" 40 ns LOW 50%; |
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| 19 | 19 |