mips_sys

added register file
Parent 8a58ba2
Stefan Schuermans

Stefan Schuermans commited on 2012-01-24 18:40:18
Showing 3 changed files, with 91 additions and 46 deletions.

mips/core.vhd
View file @ 8072c84
... ... 
@@ -29,6 +29,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
29 29
30 30 
     SIGNAL s_op1: std_logic_vector(31 DOWNTO 0);
31 31 
     SIGNAL s_op2: std_logic_vector(31 DOWNTO 0);
32 
+    SIGNAL s_res: std_logic_vector(31 DOWNTO 0);
32 33
33 34 
     COMPONENT e_mips_decoder IS
34 35 
         PORT (
... ... 
@@ -47,6 +48,20 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
47 48 
         );
48 49 
     END COMPONENT e_mips_decoder;
49 50
51 
+    COMPONENT e_mips_regs IS
52 
+        PORT (
53 
+            rst:         IN  std_logic;
54 
+            clk:         IN  std_logic;
55 
+            i_rd_a_no:   IN  std_logic_vector( 4 DOWNTO 0);
56 
+            o_rd_a_data: OUT std_logic_vector(31 DOWNTO 0);
57 
+            i_rd_b_no:   IN  std_logic_vector( 4 DOWNTO 0);
58 
+            o_rd_b_data: OUT std_logic_vector(31 DOWNTO 0);
59 
+            i_wr_no:     IN  std_logic_vector( 4 DOWNTO 0);
60 
+            i_wr_data:   IN  std_logic_vector(31 DOWNTO 0);
61 
+            i_wr_en:     IN  std_logic
62 
+        );
63 
+    END COMPONENT e_mips_regs;
64 
+
50 65 
     COMPONENT e_mips_alu IS
51 66 
         PORT (
52 67 
             i_alu: IN  t_alu;
... ... 
@@ -74,15 +89,25 @@ BEGIN
74 89 
             o_imm    => s_imm
75 90 
         );
76 91
77 
-    s_op1 <= s_src_s & s_src_s & s_src_s & s_src_s & s_src_s & s_src_s & "00";
78 
-    s_op2 <= s_src_t & s_src_t & s_src_t & s_src_t & s_src_t & s_src_t & "00";
92 
+    regs: e_mips_regs
93 
+        PORT MAP (
94 
+            rst         => rst,
95 
+            clk         => clk,
96 
+            i_rd_a_no   => s_src_s,
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+            o_rd_a_data => s_op1,
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+            i_rd_b_no   => s_src_t,
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+            o_rd_b_data => s_op2,
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+            i_wr_no     => s_dest,
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+            i_wr_data   => s_res,
102 
+            i_wr_en     => '1'
103 
+        );
79 104
80 105 
     alu: e_mips_alu
81 106 
         PORT MAP (
82 107 
             i_alu => s_alu,
83 108 
             i_op1 => s_op1,
84 109 
             i_op2 => s_op2,
85 
-            o_res => o_res
110 
+            o_res => s_res
86 111 
         );
87 112
88 113 
     p_dummy_fetch: PROCESS(rst, clk)
... ... 
@@ -94,5 +119,7 @@ BEGIN
94 119 
         END IF;
95 120 
     END PROCESS p_dummy_fetch;
96 121
122 
+    o_res <= s_res;
123 
+
97 124 
 END ARCHITECTURE a_mips_core;
98 125
mips/regs.vhd
View file @ 8072c84
... ... 
@@ -0,0 +1,51 @@
1 
+LIBRARY ieee;
2 
+USE ieee.std_logic_1164.all;
3 
+USE ieee.numeric_std.all;
4 
+USE work.mips_types.all;
5 
+
6 
+ENTITY e_mips_regs IS
7 
+    PORT (
8 
+        rst:         IN  std_logic;
9 
+        clk:         IN  std_logic;
10 
+        i_rd_a_no:   IN  std_logic_vector( 4 DOWNTO 0);
11 
+        o_rd_a_data: OUT std_logic_vector(31 DOWNTO 0);
12 
+        i_rd_b_no:   IN  std_logic_vector( 4 DOWNTO 0);
13 
+        o_rd_b_data: OUT std_logic_vector(31 DOWNTO 0);
14 
+        i_wr_no:     IN  std_logic_vector( 4 DOWNTO 0);
15 
+        i_wr_data:   IN  std_logic_vector(31 DOWNTO 0);
16 
+        i_wr_en:     IN  std_logic
17 
+    );
18 
+END ENTITY e_mips_regs;
19 
+
20 
+ARCHITECTURE a_mips_regs OF e_mips_regs IS
21 
+
22 
+    SUBTYPE t_idx IS natural RANGE 31 DOWNTO 0;
23 
+
24 
+    TYPE t_regs IS ARRAY(t_idx) OF std_logic_vector(31 DOWNTO 0);
25 
+
26 
+    SIGNAL r_regs: t_regs;
27 
+
28 
+    FUNCTION no2idx(no: std_logic_vector(4 DOWNTO 0)) RETURN natural IS
29 
+    BEGIN
30 
+        RETURN to_integer(unsigned(no));
31 
+    END FUNCTION no2idx;
32 
+
33 
+BEGIN
34 
+
35 
+    o_rd_a_data <= r_regs(no2idx(i_rd_a_no));
36 
+
37 
+    o_rd_b_data <= r_regs(no2idx(i_rd_b_no));
38 
+
39 
+    p_write: PROCESS(rst, clk)
40 
+    BEGIN
41 
+        IF rst = '1' THEN
42 
+            -- r_regs <= (OTHERS => X"00000000");
43 
+        ELSIF rising_edge(clk) THEN
44 
+            IF i_wr_en = '1' THEN
45 
+                r_regs(no2idx(i_wr_no)) <= i_wr_data;
46 
+            END IF;
47 
+        END IF;
48 
+    END PROCESS p_write;
49 
+
50 
+END ARCHITECTURE a_mips_regs;
51 
+
mips_sys.xise
View file @ 8072c84
... ... 
@@ -17,7 +17,7 @@
17 17 
   <files>
18 18 
     <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19 19 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
20 
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
20 
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
21 21 
     </file>
22 22 
     <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
23 23 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
... ... 
@@ -25,17 +25,21 @@
25 25 
     </file>
26 26 
     <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27 27 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
28 
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
28 
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
29 29 
     </file>
30 30 
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31 31 
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
32 
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
32 
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
33 33 
     </file>
34 34 
     <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
35 
-      <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
35 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
36 36 
     </file>
37 37 
     <file xil_pn:name="constraints/rst.ucf" xil_pn:type="FILE_UCF">
38 
-      <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
38 
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
39 
+    </file>
40 
+    <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
41 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
42 
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
39 43 
     </file>
40 44 
   </files>
41 45
... ... 
@@ -61,17 +65,12 @@
61 65 
     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
62 66 
     <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
63 67 
     <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
64 
-    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
65 
-    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
66 
-    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
67 68 
     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
68 
-    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
69 69 
     <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
70 70 
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
71 71 
     <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
72 72 
     <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
73 73 
     <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
74 
-    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
75 74 
     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
76 75 
     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
77 76 
     <property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/>
... ... 
@@ -86,7 +85,6 @@
86 85 
     <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
87 86 
     <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
88 87 
     <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
89 
-    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
90 88 
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
91 89 
     <property xil_pn:name="Device" xil_pn:value="xc3s700a" xil_pn:valueState="non-default"/>
92 90 
     <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
... ... 
@@ -110,7 +108,6 @@
110 108 
     <property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3A Starter Kit" xil_pn:valueState="non-default"/>
111 109 
     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
112 110 
     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
113 
-    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
114 111 
     <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
115 112 
     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
116 113 
     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
... ... 
@@ -118,7 +115,6 @@
118 115 
     <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
119 116 
     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
120 117 
     <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
121 
-    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
122 118 
     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
123 119 
     <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
124 120 
     <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
... ... 
@@ -133,8 +129,6 @@
133 129 
     <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
134 130 
     <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
135 131 
     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
136 
-    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
137 
-    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
138 132 
     <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
139 133 
     <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
140 134 
     <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
... ... 
@@ -146,13 +140,10 @@
146 140 
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
147 141 
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
148 142 
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
149 
-    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
150 143 
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
151 
-    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
152 144 
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
153 145 
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
154 146 
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
155 
-    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
156 147 
     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|e_mips_core|a_mips_core" xil_pn:valueState="non-default"/>
157 148 
     <property xil_pn:name="Implementation Top File" xil_pn:value="mips/core.vhd" xil_pn:valueState="non-default"/>
158 149 
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/e_mips_core" xil_pn:valueState="non-default"/>
... ... 
@@ -161,7 +152,6 @@
161 152 
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
162 153 
     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
163 154 
     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
164 
-    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
165 155 
     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
166 156 
     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
167 157 
     <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
... ... 
@@ -169,7 +159,6 @@
169 159 
     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
170 160 
     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
171 161 
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
172 
-    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
173 162 
     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
174 163 
     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
175 164 
     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
... ... 
@@ -177,9 +166,7 @@
177 166 
     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
178 167 
     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
179 168 
     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
180 
-    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
181 169 
     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
182 
-    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
183 170 
     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
184 171 
     <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
185 172 
     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
... ... 
@@ -204,7 +191,6 @@
204 191 
     <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
205 192 
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
206 193 
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
207 
-    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
208 194 
     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
209 195 
     <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
210 196 
     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
... ... 
@@ -215,18 +201,14 @@
215 201 
     <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
216 202 
     <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
217 203 
     <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
218 
-    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
219 204 
     <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
220 
-    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
221 205 
     <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
222 206 
     <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
223 207 
     <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
224 
-    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
225 208 
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
226 209 
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
227 210 
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
228 211 
     <property xil_pn:name="Output File Name" xil_pn:value="e_mips_core" xil_pn:valueState="default"/>
229 
-    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
230 212 
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
231 213 
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
232 214 
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
... ... 
@@ -246,7 +228,6 @@
246 228 
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
247 229 
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
248 230 
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
249 
-    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
250 231 
     <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
251 232 
     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
252 233 
     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
... ... 
@@ -302,7 +283,6 @@
302 283 
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
303 284 
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
304 285 
     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
305 
-    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
306 286 
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
307 287 
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
308 288 
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
... ... 
@@ -313,17 +293,14 @@
313 293 
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
314 294 
     <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
315 295 
     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
316 
-    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
317 296 
     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
318 297 
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
319 298 
     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
320 299 
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
321 
-    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
322 300 
     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
323 301 
     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
324 302 
     <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
325 303 
     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
326 
-    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
327 304 
     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
328 305 
     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
329 306 
     <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
... ... 
@@ -332,36 +309,26 @@
332 309 
     <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
333 310 
     <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
334 311 
     <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
335 
-    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
336 312 
     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
337 313 
     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
338 314 
     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
339 
-    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
340 
-    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
341 
-    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
342 
-    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
343 
-    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
344 315 
     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
345 
-    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
346 
-    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
347 316 
     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
348 317 
     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
349 318 
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
350 319 
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
351 320 
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
352 
-    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
321 
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
353 322 
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
354 323 
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
355 324 
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
356 325 
     <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
357 326 
     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
358 
-    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
359 327 
     <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
360 328 
     <property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
361 329 
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
362 330 
     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
363 331 
     <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
364 
-    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
365 332 
     <!--                                                                                  -->
366 333 
     <!-- The following properties are for internal use only. These should not be modified.-->
367 334 
     <!--                                                                                  -->
368 335