implemented switches (5e29ab5) - mips_sys · BlinkenArea

implemented switches

Stefan Schuermans commited on 2012-02-12 20:47:12
Showing 11 changed files, with 254 additions and 43 deletions.

constraints/rst.ucf a5de855..0000000
constraints/switches.ucf 0000000..a731961
fw/Makefile 371c8ff..104c4fd
fw/main.c 3503bec..4bc19b5
fw/switches.c 0000000..0ce6b7f
fw/switches.h 0000000..7446f4f
io/switches.vhd 0000000..57dfa83
io/switches_pins.vhd 0000000..7d4ed33
mips_sys.xise d77af8f..1fa57c0
system/system.vhd 6d9d80f..3803e59
test/testbed.vhd ab6db10..2213450

constraints/rst.ucf

...	...	@@ -1 +0,0 @@
1		-NET "rst" LOC = "U15" \| IOSTANDARD = LVTTL \| PULLDOWN; # button west

constraints/switches.ucf

View file @ 5e29ab5

...	...	@@ -0,0 +1,11 @@
	1	+NET "pin_i_switches_sw[3]" LOC = "T9" \| IOSTANDARD = LVTTL \| PULLUP;
	2	+NET "pin_i_switches_sw[2]" LOC = "U8" \| IOSTANDARD = LVTTL \| PULLUP;
	3	+NET "pin_i_switches_sw[1]" LOC = "U10"\| IOSTANDARD = LVTTL \| PULLUP;
	4	+NET "pin_i_switches_sw[0]" LOC = "V8" \| IOSTANDARD = LVTTL \| PULLUP;
	5	+NET "pin_i_switches_east" LOC = "T16" \| IOSTANDARD = LVTTL \| PULLDOWN;
	6	+NET "pin_i_switches_north" LOC = "T14" \| IOSTANDARD = LVTTL \| PULLDOWN;
	7	+NET "pin_i_switches_south" LOC = "T15" \| IOSTANDARD = LVTTL \| PULLDOWN;
	8	+NET "pin_i_switches_west" LOC = "U15" \| IOSTANDARD = LVTTL \| PULLDOWN;
	9	+NET "pin_i_switches_center" LOC = "R13" \| IOSTANDARD = LVTTL \| PULLDOWN;
	10	+NET "pin_i_switches_rot_a" LOC = "T13" \| IOSTANDARD = LVTTL \| PULLUP;
	11	+NET "pin_i_switches_rot_b" LOC = "R14" \| IOSTANDARD = LVTTL \| PULLUP;

fw/Makefile

View file @ 5e29ab5

...	...	@@ -1,4 +1,4 @@
1		-SRCS=cyc_cnt.c lcd.c leds.c main.c
	1	+SRCS=cyc_cnt.c lcd.c leds.c main.c switches.c
2	2
3	3	PERL=perl
4	4	CC=mipsel-elf-gcc

fw/main.c

View file @ 5e29ab5

@@ -1,6 +1,7 @@
 #include "cyc_cnt.h"
 #include "lcd.h"
 #include "leds.h"
+#include "switches.h"
 
 const int myconst = 0x12345678;
 
@@ -8,9 +9,28 @@ int myvar = 0x11223344;
 
 volatile int data[100];
 
+void switches(void)
+{
+  lcd_chr(1, 0, switches_get_state(sw_0) ? '0' : ' ');
+  lcd_chr(1, 1, switches_get_state(sw_1) ? '1' : ' ');
+  lcd_chr(1, 2, switches_get_state(sw_2) ? '2' : ' ');
+  lcd_chr(1, 3, switches_get_state(sw_3) ? '3' : ' ');
+  lcd_chr(1, 4, switches_get_state(sw_east) ? 'E' : ' ');
+  lcd_chr(1, 5, switches_get_state(sw_north) ? 'N' : ' ');
+  lcd_chr(1, 6, switches_get_state(sw_south) ? 'S' : ' ');
+  lcd_chr(1, 7, switches_get_state(sw_west) ? 'W' : ' ');
+  lcd_chr(1, 8, switches_get_state(sw_center) ? 'C' : ' ');
+  lcd_chr(1, 9, switches_get_state(sw_rot_a) ? 'a' : ' ');
+  lcd_chr(1, 10, switches_get_state(sw_rot_b) ? 'b' : ' ');
+}
+
 void delay(void)
 {
-  cyc_cnt_delay_ms(200);
+  unsigned int i;
+  for (i = 0; i < 10; ++i) {
+    switches();
+    cyc_cnt_delay_ms(20);
+  }
 }
 
 int main()
@@ -21,6 +41,8 @@ int main()
     data[i] = i;
 
   lcd_init();
+  lcd_str(0, "MIPS I system");
+  lcd_str(1, "");
 
   while (1) {
     for (i = 0x1; i < 0x80; i <<= 1) {

fw/switches.c

View file @ 5e29ab5

...	...	@@ -0,0 +1,15 @@
	1	+#include "switches.h"
	2	+
	3	+static volatile unsigned int *const switches_ptr =
	4	+ (volatile unsigned int *)0x80000200;
	5	+
	6	+/**
	7	+ * @brief get state of switch
	8	+ * @param[in] sw swich identifier
	9	+ * @return switch state
	10	+ */
	11	+int switches_get_state(t_switch sw)
	12	+{
	13	+ return switches_ptr[0] >> sw & 1;
	14	+}
	15	+

fw/switches.h

View file @ 5e29ab5

...	...	@@ -0,0 +1,27 @@
	1	+#ifndef SWITCHES_H
	2	+#define SWITCHES_H
	3	+
	4	+/** switch identifier */
	5	+typedef enum e_switch {
	6	+ sw_0 = 0,
	7	+ sw_1 = 1,
	8	+ sw_2 = 2,
	9	+ sw_3 = 3,
	10	+ sw_east = 8,
	11	+ sw_north = 9,
	12	+ sw_south = 10,
	13	+ sw_west = 11,
	14	+ sw_center = 16,
	15	+ sw_rot_a = 24,
	16	+ sw_rot_b = 25
	17	+} t_switch;
	18	+
	19	+/**
	20	+ * @brief get state of switch
	21	+ * @param[in] sw swich identifier
	22	+ * @return switch state
	23	+ */
	24	+int switches_get_state(t_switch sw);
	25	+
	26	+#endif /* #ifndef SWITCHES_H */
	27	+

io/switches.vhd

View file @ 5e29ab5

...	...	@@ -0,0 +1,89 @@
	1	+LIBRARY IEEE;
	2	+USE IEEE.STD_LOGIC_1164.ALL;
	3	+USE IEEE.NUMERIC_STD.ALL;
	4	+USE work.io_switches_pins.all;
	5	+
	6	+ENTITY e_io_switches IS
	7	+ PORT (
	8	+ rst: IN std_logic;
	9	+ clk: IN std_logic;
	10	+ i_addr: IN std_logic_vector( 0 DOWNTO 0);
	11	+ o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
	12	+ pin_i_switches: IN t_io_switches_pins
	13	+ );
	14	+END ENTITY e_io_switches;
	15	+
	16	+ARCHITECTURE a_io_switches OF e_io_switches IS
	17	+
	18	+ SIGNAL n_sample: std_logic_vector(1 DOWNTO 0);
	19	+ SIGNAL r_sample: std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
	20	+ SIGNAL r_prev: std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
	21	+ SIGNAL n_cnt: std_logic_vector(31 DOWNTO 0);
	22	+ SIGNAL r_cnt: std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
	23	+
	24	+BEGIN
	25	+
	26	+ p_sample: PROCESS(pin_i_switches)
	27	+ BEGIN
	28	+ -- de-gray-code rotary inputs
	29	+ IF pin_i_switches.rot_b = '1' THEN
	30	+ IF pin_i_switches.rot_a = '1' THEN
	31	+ n_sample <= "10";
	32	+ ELSE
	33	+ n_sample <= "11";
	34	+ END IF;
	35	+ ELSE
	36	+ IF pin_i_switches.rot_a = '1' THEN
	37	+ n_sample <= "01";
	38	+ ELSE
	39	+ n_sample <= "00";
	40	+ END IF;
	41	+ END IF;
	42	+ END PROCESS p_sample;
	43	+
	44	+ p_cnt: PROCESS(r_sample, r_prev, r_cnt)
	45	+ VARIABLE v_delta: signed(1 DOWNTO 0);
	46	+ BEGIN
	47	+ v_delta := signed(r_sample) - signed(r_prev);
	48	+ n_cnt <= std_logic_vector(signed(r_cnt) + v_delta);
	49	+ END PROCESS p_cnt;
	50	+
	51	+ p_sync: PROCESS(rst, clk)
	52	+ BEGIN
	53	+ IF rst = '1' THEN
	54	+ r_sample <= (OTHERS => '0');
	55	+ r_prev <= (OTHERS => '0');
	56	+ r_cnt <= (OTHERS => '0');
	57	+ ELSIF rising_edge(clk) THEN
	58	+ r_sample <= n_sample;
	59	+ r_prev <= r_sample;
	60	+ r_cnt <= n_cnt;
	61	+ END IF;
	62	+ END PROCESS p_sync;
	63	+
	64	+ p_read: PROCESS(rst, clk)
	65	+ BEGIN
	66	+ IF rst = '1' THEN
	67	+ o_rd_data <= (OTHERS => '0');
	68	+ ELSIF rising_edge(clk) THEN
	69	+ IF i_addr = "0" THEN
	70	+ o_rd_data( 3 DOWNTO 0) <= pin_i_switches.sw;
	71	+ o_rd_data( 7 DOWNTO 4) <= (OTHERS => '0');
	72	+ o_rd_data( 8) <= pin_i_switches.east;
	73	+ o_rd_data( 9) <= pin_i_switches.north;
	74	+ o_rd_data(10) <= pin_i_switches.south;
	75	+ o_rd_data(11) <= pin_i_switches.west;
	76	+ o_rd_data(15 DOWNTO 12) <= (OTHERS => '0');
	77	+ o_rd_data(16) <= pin_i_switches.center;
	78	+ o_rd_data(23 DOWNTO 17) <= (OTHERS => '0');
	79	+ o_rd_data(24) <= pin_i_switches.rot_a;
	80	+ o_rd_data(25) <= pin_i_switches.rot_b;
	81	+ o_rd_data(31 DOWNTO 26) <= (OTHERS => '0');
	82	+ ELSE
	83	+ o_rd_data <= r_cnt;
	84	+ END IF;
	85	+ END IF;
	86	+ END PROCESS p_read;
	87	+
	88	+END ARCHITECTURE a_io_switches;
	89	+

io/switches_pins.vhd

View file @ 5e29ab5

...	...	@@ -0,0 +1,20 @@
	1	+LIBRARY ieee;
	2	+USE ieee.std_logic_1164.all;
	3	+USE ieee.numeric_std.all;
	4	+
	5	+PACKAGE io_switches_pins IS
	6	+
	7	+ TYPE t_io_switches_pins IS
	8	+ RECORD
	9	+ sw: std_logic_vector(3 DOWNTO 0);
	10	+ east: std_logic;
	11	+ north: std_logic;
	12	+ south: std_logic;
	13	+ west: std_logic;
	14	+ center: std_logic;
	15	+ rot_a: std_logic;
	16	+ rot_b: std_logic;
	17	+ END RECORD;
	18	+
	19	+END PACKAGE io_switches_pins;
	20	+

mips_sys.xise

View file @ 5e29ab5

@@ -28,8 +28,8 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
@@ -52,22 +52,22 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
     </file>
     <file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@@ -75,39 +75,47 @@
     <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="constraints/rst.ucf" xil_pn:type="FILE_UCF">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+    </file>
+    <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+    </file>
+    <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
-    <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
-    <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+    <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
-    <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+    <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+    </file>
+    <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
 
@@ -423,8 +431,8 @@
   <bindings>
     <binding xil_pn:location="/e_system" xil_pn:name="constraints/leds.ucf"/>
     <binding xil_pn:location="/e_system" xil_pn:name="constraints/clk.ucf"/>
-    <binding xil_pn:location="/e_system" xil_pn:name="constraints/rst.ucf"/>
     <binding xil_pn:location="/e_system" xil_pn:name="constraints/lcd.ucf"/>
+    <binding xil_pn:location="/e_system" xil_pn:name="constraints/switches.ucf"/>
   </bindings>
 
   <libraries/>

system/system.vhd

View file @ 5e29ab5

@@ -2,18 +2,21 @@ LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.NUMERIC_STD.ALL;
 USE work.io_lcd_pins.all;
+USE work.io_switches_pins.all;
 
 ENTITY e_system IS
     PORT (
-        rst:        IN  std_logic;
         clk:            IN  std_logic;
         pin_o_leds:     OUT std_logic_vector(7 DOWNTO 0);
-        pin_o_lcd:  OUT t_io_lcd_pins
+        pin_o_lcd:      OUT t_io_lcd_pins;
+        pin_i_switches: IN  t_io_switches_pins
     );
 END ENTITY e_system;
 
 ARCHITECTURE a_system OF e_system IS
 
+    SIGNAL rst: std_logic := '0';
+
     SIGNAL s_instr_addr:   std_logic_vector(31 DOWNTO 0);
     SIGNAL s_instr_data:   std_logic_vector(31 DOWNTO 0);
     SIGNAL s_dbus_addr:    std_logic_vector(31 DOWNTO 0);
@@ -30,6 +33,8 @@ ARCHITECTURE a_system OF e_system IS
     SIGNAL s_lcd_rd_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_lcd_wr_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_lcd_wr_en:   std_logic_vector( 3 DOWNTO 0);
+    SIGNAL s_switches_addr:    std_logic_vector( 2 DOWNTO 0);
+    SIGNAL s_switches_rd_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_cyc_cnt_rd_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_cyc_cnt_wr_data: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_cyc_cnt_wr_en:   std_logic;
@@ -133,6 +138,16 @@ ARCHITECTURE a_system OF e_system IS
         );
     END COMPONENT e_io_lcd;
 
+    COMPONENT e_io_switches IS
+        PORT (
+            rst:            IN  std_logic;
+            clk:            IN  std_logic;
+            i_addr:         IN  std_logic_vector( 0 DOWNTO 0);
+            o_rd_data:      OUT std_logic_vector(31 DOWNTO 0);
+            pin_i_switches: IN  t_io_switches_pins
+        );
+    END COMPONENT e_io_switches;
+
     COMPONENT e_io_cyc_cnt IS
         PORT (
             rst:       IN  std_logic;
@@ -202,6 +217,9 @@ BEGIN
                     s_dbus_rd_data <= s_lcd_rd_data;
                     s_lcd_wr_data  <= s_dbus_wr_data;
                     s_lcd_wr_en    <= s_dbus_wr_en;
+                WHEN X"02" =>
+                    s_dbus_rd_data  <= s_switches_rd_data;
+                    s_switches_addr <= s_dbus_addr(2 DOWNTO 0);
                 WHEN X"10" =>
                     s_dbus_rd_data    <= s_cyc_cnt_rd_data;
                     s_cyc_cnt_wr_data <= s_dbus_wr_data;
@@ -279,6 +297,15 @@ BEGIN
             pin_o_lcd => pin_o_lcd
         );
 
+    switches: e_io_switches
+        PORT MAP (
+            rst            => rst,
+            clk            => clk,
+            i_addr         => s_switches_addr(2 DOWNTO 2),
+            o_rd_data      => s_switches_rd_data,
+            pin_i_switches => pin_i_switches
+        );
+
     cyc_cnt: e_io_cyc_cnt
         PORT MAP (
             rst       => rst,

test/testbed.vhd

View file @ 5e29ab5

@@ -3,6 +3,7 @@ USE ieee.std_logic_1164.all;
 USE ieee.numeric_std.all;
 USE std.textio.all;
 USE work.io_lcd_pins.all;
+USE work.io_switches_pins.all;
 
 ENTITY e_testbed IS
 END ENTITY e_testbed;
@@ -11,14 +12,13 @@ ARCHITECTURE a_testbed OF e_testbed IS
 
     COMPONENT e_system IS
         PORT (
-            rst:        IN  std_logic;
             clk:            IN  std_logic;
             pin_o_leds:     OUT std_logic_vector(7 DOWNTO 0);
-            pin_o_lcd:  OUT t_io_lcd_pins
+            pin_o_lcd:      OUT t_io_lcd_pins;
+            pin_i_switches: IN  t_io_switches_pins
         );
     END COMPONENT e_system;
 
-    SIGNAL s_rst:    std_logic;
     SIGNAL s_clk:    std_logic;
     SIGNAL pin_leds: std_logic_vector(7 DOWNTO 0);
     SIGNAL pin_lcd:  t_io_lcd_pins;
@@ -28,21 +28,14 @@ BEGIN
     system: e_system
         PORT MAP (
             clk            => s_clk,
-            rst        => s_rst,
             pin_o_leds     => pin_leds,
-            pin_o_lcd  => pin_lcd
+            pin_o_lcd      => pin_lcd,
+            pin_i_switches => (sw => (OTHERS => '0'), OTHERS => '0')
         );
 
     p_rst_clk: PROCESS
     BEGIN
-        s_rst        <= '0';
         s_clk        <= '0';
-
-        WAIT FOR 10 ns;
-        s_rst <= '1';
-        WAIT FOR 10 ns;
-        s_rst <= '0';
-
         WHILE TRUE LOOP
             WAIT FOR 10 ns;
             s_clk <= '1';


...	...	@@ -0,0 +1,11 @@
	1	+NET "pin_i_switches_sw[3]" LOC = "T9" \| IOSTANDARD = LVTTL \| PULLUP;
	2	+NET "pin_i_switches_sw[2]" LOC = "U8" \| IOSTANDARD = LVTTL \| PULLUP;
	3	+NET "pin_i_switches_sw[1]" LOC = "U10"\| IOSTANDARD = LVTTL \| PULLUP;
	4	+NET "pin_i_switches_sw[0]" LOC = "V8" \| IOSTANDARD = LVTTL \| PULLUP;
	5	+NET "pin_i_switches_east" LOC = "T16" \| IOSTANDARD = LVTTL \| PULLDOWN;
	6	+NET "pin_i_switches_north" LOC = "T14" \| IOSTANDARD = LVTTL \| PULLDOWN;
	7	+NET "pin_i_switches_south" LOC = "T15" \| IOSTANDARD = LVTTL \| PULLDOWN;
	8	+NET "pin_i_switches_west" LOC = "U15" \| IOSTANDARD = LVTTL \| PULLDOWN;
	9	+NET "pin_i_switches_center" LOC = "R13" \| IOSTANDARD = LVTTL \| PULLDOWN;
	10	+NET "pin_i_switches_rot_a" LOC = "T13" \| IOSTANDARD = LVTTL \| PULLUP;
	11	+NET "pin_i_switches_rot_b" LOC = "R14" \| IOSTANDARD = LVTTL \| PULLUP;

...	...	@@ -1,6 +1,7 @@
1	1	#include "cyc_cnt.h"
2	2	#include "lcd.h"
3	3	#include "leds.h"
	4	+#include "switches.h"
4	5
5	6	const int myconst = 0x12345678;
6	7
...	...	@@ -8,9 +9,28 @@ int myvar = 0x11223344;
8	9
9	10	volatile int data[100];
10	11
	12	+void switches(void)
	13	+{
	14	+ lcd_chr(1, 0, switches_get_state(sw_0) ? '0' : ' ');
	15	+ lcd_chr(1, 1, switches_get_state(sw_1) ? '1' : ' ');
	16	+ lcd_chr(1, 2, switches_get_state(sw_2) ? '2' : ' ');
	17	+ lcd_chr(1, 3, switches_get_state(sw_3) ? '3' : ' ');
	18	+ lcd_chr(1, 4, switches_get_state(sw_east) ? 'E' : ' ');
	19	+ lcd_chr(1, 5, switches_get_state(sw_north) ? 'N' : ' ');
	20	+ lcd_chr(1, 6, switches_get_state(sw_south) ? 'S' : ' ');
	21	+ lcd_chr(1, 7, switches_get_state(sw_west) ? 'W' : ' ');
	22	+ lcd_chr(1, 8, switches_get_state(sw_center) ? 'C' : ' ');
	23	+ lcd_chr(1, 9, switches_get_state(sw_rot_a) ? 'a' : ' ');
	24	+ lcd_chr(1, 10, switches_get_state(sw_rot_b) ? 'b' : ' ');
	25	+}
	26	+
11	27	void delay(void)
12	28	{
13		- cyc_cnt_delay_ms(200);
	29	+ unsigned int i;
	30	+ for (i = 0; i < 10; ++i) {
	31	+ switches();
	32	+ cyc_cnt_delay_ms(20);
	33	+ }
14	34	}
15	35
16	36	int main()
...	...	@@ -21,6 +41,8 @@ int main()
21	41	data[i] = i;
22	42
23	43	lcd_init();
	44	+ lcd_str(0, "MIPS I system");
	45	+ lcd_str(1, "");
24	46
25	47	while (1) {
26	48	for (i = 0x1; i < 0x80; i <<= 1) {

...	...	@@ -28,8 +28,8 @@
28	28	<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
29	29	</file>
30	30	<file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
32		- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
	31	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
	32	+ <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
33	33	</file>
34	34	<file xil_pn:name="mips/regs.vhd" xil_pn:type="FILE_VHDL">
35	35	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
...	...	@@ -52,22 +52,22 @@
52	52	<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
53	53	</file>
54	54	<file xil_pn:name="system/system.vhd" xil_pn:type="FILE_VHDL">
55		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
56		- <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
	55	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
	56	+ <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
57	57	</file>
58	58	<file xil_pn:name="test/testbed.vhd" xil_pn:type="FILE_VHDL">
59		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
	59	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
60	60	<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
61	61	<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
62	62	<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
63	63	</file>
64	64	<file xil_pn:name="fw/rom.vhd" xil_pn:type="FILE_VHDL">
65		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
66		- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
	65	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
	66	+ <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
67	67	</file>
68	68	<file xil_pn:name="io/leds.vhd" xil_pn:type="FILE_VHDL">
69		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
70		- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
	69	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
	70	+ <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
71	71	</file>
72	72	<file xil_pn:name="constraints/leds.ucf" xil_pn:type="FILE_UCF">
73	73	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
...	...	@@ -75,39 +75,47 @@
75	75	<file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
76	76	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
77	77	</file>
78		- <file xil_pn:name="constraints/rst.ucf" xil_pn:type="FILE_UCF">
79		- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
80		- </file>
81	78	<file xil_pn:name="io/cyc_cnt.vhd" xil_pn:type="FILE_VHDL">
82		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
83		- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
	79	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
	80	+ <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
84	81	</file>
85	82	<file xil_pn:name="io/lcd.vhd" xil_pn:type="FILE_VHDL">
86		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
87		- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
	83	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
	84	+ <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
88	85	</file>
89	86	<file xil_pn:name="io/lcd_pins.vhd" xil_pn:type="FILE_VHDL">
90		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
91		- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
	87	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
	88	+ <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
92	89	</file>
93	90	<file xil_pn:name="constraints/lcd.ucf" xil_pn:type="FILE_UCF">
94	91	<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
95	92	</file>
96	93	<file xil_pn:name="fw/ram.0.vhd" xil_pn:type="FILE_VHDL">
	94	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
	95	+ <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
	96	+ </file>
	97	+ <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
	98	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
	99	+ <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
	100	+ </file>
	101	+ <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
97	102	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
98	103	<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
99	104	</file>
100		- <file xil_pn:name="fw/ram.1.vhd" xil_pn:type="FILE_VHDL">
	105	+ <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
101	106	<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
102	107	<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
103	108	</file>
104		- <file xil_pn:name="fw/ram.2.vhd" xil_pn:type="FILE_VHDL">
105		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
106		- <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
	109	+ <file xil_pn:name="io/switches_pins.vhd" xil_pn:type="FILE_VHDL">
	110	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
	111	+ <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
107	112	</file>
108		- <file xil_pn:name="fw/ram.3.vhd" xil_pn:type="FILE_VHDL">
109		- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
110		- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
	113	+ <file xil_pn:name="io/switches.vhd" xil_pn:type="FILE_VHDL">
	114	+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
	115	+ <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
	116	+ </file>
	117	+ <file xil_pn:name="constraints/switches.ucf" xil_pn:type="FILE_UCF">
	118	+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
111	119	</file>
112	120	</files>
113	121
...	...	@@ -423,8 +431,8 @@
423	431	<bindings>
424	432	<binding xil_pn:location="/e_system" xil_pn:name="constraints/leds.ucf"/>
425	433	<binding xil_pn:location="/e_system" xil_pn:name="constraints/clk.ucf"/>
426		- <binding xil_pn:location="/e_system" xil_pn:name="constraints/rst.ucf"/>
427	434	<binding xil_pn:location="/e_system" xil_pn:name="constraints/lcd.ucf"/>
	435	+ <binding xil_pn:location="/e_system" xil_pn:name="constraints/switches.ucf"/>
428	436	</bindings>
429	437
430	438	<libraries/>

...	...	@@ -2,18 +2,21 @@ LIBRARY IEEE;
2	2	USE IEEE.STD_LOGIC_1164.ALL;
3	3	USE IEEE.NUMERIC_STD.ALL;
4	4	USE work.io_lcd_pins.all;
	5	+USE work.io_switches_pins.all;
5	6
6	7	ENTITY e_system IS
7	8	PORT (
8		- rst: IN std_logic;
9	9	clk: IN std_logic;
10	10	pin_o_leds: OUT std_logic_vector(7 DOWNTO 0);
11		- pin_o_lcd: OUT t_io_lcd_pins
	11	+ pin_o_lcd: OUT t_io_lcd_pins;
	12	+ pin_i_switches: IN t_io_switches_pins
12	13	);
13	14	END ENTITY e_system;
14	15
15	16	ARCHITECTURE a_system OF e_system IS
16	17
	18	+ SIGNAL rst: std_logic := '0';
	19	+
17	20	SIGNAL s_instr_addr: std_logic_vector(31 DOWNTO 0);
18	21	SIGNAL s_instr_data: std_logic_vector(31 DOWNTO 0);
19	22	SIGNAL s_dbus_addr: std_logic_vector(31 DOWNTO 0);
...	...	@@ -30,6 +33,8 @@ ARCHITECTURE a_system OF e_system IS
30	33	SIGNAL s_lcd_rd_data: std_logic_vector(31 DOWNTO 0);
31	34	SIGNAL s_lcd_wr_data: std_logic_vector(31 DOWNTO 0);
32	35	SIGNAL s_lcd_wr_en: std_logic_vector( 3 DOWNTO 0);
	36	+ SIGNAL s_switches_addr: std_logic_vector( 2 DOWNTO 0);
	37	+ SIGNAL s_switches_rd_data: std_logic_vector(31 DOWNTO 0);
33	38	SIGNAL s_cyc_cnt_rd_data: std_logic_vector(31 DOWNTO 0);
34	39	SIGNAL s_cyc_cnt_wr_data: std_logic_vector(31 DOWNTO 0);
35	40	SIGNAL s_cyc_cnt_wr_en: std_logic;
...	...	@@ -133,6 +138,16 @@ ARCHITECTURE a_system OF e_system IS
133	138	);
134	139	END COMPONENT e_io_lcd;
135	140
	141	+ COMPONENT e_io_switches IS
	142	+ PORT (
	143	+ rst: IN std_logic;
	144	+ clk: IN std_logic;
	145	+ i_addr: IN std_logic_vector( 0 DOWNTO 0);
	146	+ o_rd_data: OUT std_logic_vector(31 DOWNTO 0);
	147	+ pin_i_switches: IN t_io_switches_pins
	148	+ );
	149	+ END COMPONENT e_io_switches;
	150	+
136	151	COMPONENT e_io_cyc_cnt IS
137	152	PORT (
138	153	rst: IN std_logic;
...	...	@@ -202,6 +217,9 @@ BEGIN
202	217	s_dbus_rd_data <= s_lcd_rd_data;
203	218	s_lcd_wr_data <= s_dbus_wr_data;
204	219	s_lcd_wr_en <= s_dbus_wr_en;
	220	+ WHEN X"02" =>
	221	+ s_dbus_rd_data <= s_switches_rd_data;
	222	+ s_switches_addr <= s_dbus_addr(2 DOWNTO 0);
205	223	WHEN X"10" =>
206	224	s_dbus_rd_data <= s_cyc_cnt_rd_data;
207	225	s_cyc_cnt_wr_data <= s_dbus_wr_data;
...	...	@@ -279,6 +297,15 @@ BEGIN
279	297	pin_o_lcd => pin_o_lcd
280	298	);
281	299
	300	+ switches: e_io_switches
	301	+ PORT MAP (
	302	+ rst => rst,
	303	+ clk => clk,
	304	+ i_addr => s_switches_addr(2 DOWNTO 2),
	305	+ o_rd_data => s_switches_rd_data,
	306	+ pin_i_switches => pin_i_switches
	307	+ );
	308	+
282	309	cyc_cnt: e_io_cyc_cnt
283	310	PORT MAP (
284	311	rst => rst,

...	...	@@ -3,6 +3,7 @@ USE ieee.std_logic_1164.all;
3	3	USE ieee.numeric_std.all;
4	4	USE std.textio.all;
5	5	USE work.io_lcd_pins.all;
	6	+USE work.io_switches_pins.all;
6	7
7	8	ENTITY e_testbed IS
8	9	END ENTITY e_testbed;
...	...	@@ -11,14 +12,13 @@ ARCHITECTURE a_testbed OF e_testbed IS
11	12
12	13	COMPONENT e_system IS
13	14	PORT (
14		- rst: IN std_logic;
15	15	clk: IN std_logic;
16	16	pin_o_leds: OUT std_logic_vector(7 DOWNTO 0);
17		- pin_o_lcd: OUT t_io_lcd_pins
	17	+ pin_o_lcd: OUT t_io_lcd_pins;
	18	+ pin_i_switches: IN t_io_switches_pins
18	19	);
19	20	END COMPONENT e_system;
20	21
21		- SIGNAL s_rst: std_logic;
22	22	SIGNAL s_clk: std_logic;
23	23	SIGNAL pin_leds: std_logic_vector(7 DOWNTO 0);
24	24	SIGNAL pin_lcd: t_io_lcd_pins;
...	...	@@ -28,21 +28,14 @@ BEGIN
28	28	system: e_system
29	29	PORT MAP (
30	30	clk => s_clk,
31		- rst => s_rst,
32	31	pin_o_leds => pin_leds,
33		- pin_o_lcd => pin_lcd
	32	+ pin_o_lcd => pin_lcd,
	33	+ pin_i_switches => (sw => (OTHERS => '0'), OTHERS => '0')
34	34	);
35	35
36	36	p_rst_clk: PROCESS
37	37	BEGIN
38		- s_rst <= '0';
39	38	s_clk <= '0';
40		-
41		- WAIT FOR 10 ns;
42		- s_rst <= '1';
43		- WAIT FOR 10 ns;
44		- s_rst <= '0';
45		-
46	39	WHILE TRUE LOOP
47	40	WAIT FOR 10 ns;
48	41	s_clk <= '1';
49	42