mips_sys

start of MIPS core: begin of decoder and ALU
Stefan Schuermans

Stefan Schuermans commited on 2012-01-23 22:06:18
Showing 8 changed files, with 828 additions and 0 deletions.

.gitignore
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+*.bld
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+*.cmd_log
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+*.csv
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+*.filter
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+*.gise
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+*.html
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+*.log
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+*.lso
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+*.map
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+*.mrp
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+*.ncd
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+*.ngc
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+*.ngd
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+*.ngm
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+*.ngr
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+*.pad
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+*.par
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+*.pcf
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+*.prj
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+*.ptwx
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+*.stx
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+*.syr
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+*.tcl
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+*.twr
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+*.twx
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+*.txt
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+*.unroutes
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+*.xml
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+*.xpi
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+*.xrpt
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+*.xst
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+.lso
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+_ngo
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+_xmsgs
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+fuse.*
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+fuseRelaunch.*
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+impact_impact.xwbt
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+ise_impact.cmd
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+isim
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+isim.*
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+iseconfig
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+planAhead_run_*
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+smartxplorer_results
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+xilinxsim.ini
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+xlnx_auto_0_xdb
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+xst
constraints/clk.ucf
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+NET "clk" LOC = "E12" | IOSTANDARD = LVCMOS33 | TNM_NET = clk;
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+TIMESPEC TS_clk = PERIOD "clk" 20 ns HIGH 50%;
constraints/rst.ucf
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+NET "rst" LOC = "U15"  | IOSTANDARD = LVTTL | PULLDOWN; # button west
mips/alu.vhd
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+LIBRARY ieee;
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+USE ieee.std_logic_1164.all;
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+USE ieee.numeric_std.all;
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+USE work.mips_types.all;
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+
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+ENTITY e_mips_alu IS
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+    PORT (
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+        i_alu: IN  t_alu;
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+        i_op1: IN  std_logic_vector(31 DOWNTO 0);
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+        i_op2: IN  std_logic_vector(31 DOWNTO 0);
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+        o_res: OUT std_logic_vector(31 DOWNTO 0)
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+    );
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+END ENTITY e_mips_alu;
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+
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+ARCHITECTURE a_mips_alu OF e_mips_alu IS
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+
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+BEGIN
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+
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+    p_alu: PROCESS(i_alu, i_op1, i_op2)
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+        VARIABLE v_op1_s: signed(31 DOWNTO 0);
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+        VARIABLE v_op2_s: signed(31 DOWNTO 0);
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+        VARIABLE v_op1_u: unsigned(31 DOWNTO 0);
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+        VARIABLE v_op2_u: unsigned(31 DOWNTO 0);
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+        VARIABLE v_int5:  integer RANGE 31 DOWNTO 0;
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+        VARIABLE v_tmp64: std_logic_vector(63 DOWNTO 0);
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+    BEGIN
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+        v_op1_s := signed(i_op1);
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+        v_op2_s := signed(i_op2);
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+        v_op1_u := unsigned(i_op1);
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+        v_op2_u := unsigned(i_op2);
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+        CASE i_alu IS
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+            WHEN alu_add => o_res <= std_logic_vector(v_op1_s + v_op2_s);
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+            WHEN alu_and => o_res <= i_op1 AND i_op2;
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+            WHEN alu_nor => o_res <= i_op1 NOR i_op2;
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+            WHEN alu_or  => o_res <= i_op1 OR i_op2;
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+            WHEN alu_sub => o_res <= std_logic_vector(v_op1_s - v_op2_s);
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+            WHEN alu_sll => IF i_op2(31 DOWNTO 5) = X"000000" & "000" THEN
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+                                v_int5  := to_integer(v_op2_u(4 DOWNTO 0));
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+                                v_tmp64 := i_op1 & X"00000000";
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+                                o_res   <= v_tmp64(v_int5 + 31 DOWNTO v_int5);
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+                            ELSE
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+                                o_res   <= X"00000000";
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+                            END IF;
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+            WHEN alu_sra => IF i_op2(31 DOWNTO 5) = X"000000" & "000" THEN
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+                                v_int5  := to_integer(v_op2_u(4 DOWNTO 0));
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+                                IF i_op1(31) = '1' THEN
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+                                    v_tmp64 := X"FFFFFFFF" & i_op1;
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+                                ELSE
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+                                    v_tmp64 := X"00000000" & i_op1;
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+                                END IF;
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+                                o_res   <= v_tmp64(63 - v_int5 DOWNTO 32 - v_int5);
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+                            ELSE
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+                                o_res   <= X"00000000";
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+                            END IF;
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+            WHEN alu_srl => IF i_op2(31 DOWNTO 5) = X"000000" & "000" THEN
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+                                v_int5  := to_integer(v_op2_u(4 DOWNTO 0));
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+                                v_tmp64 := X"00000000" & i_op1;
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+                                o_res   <= v_tmp64(63 - v_int5 DOWNTO 32 - v_int5);
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+                            ELSE
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+                                o_res   <= X"00000000";
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+                            END IF;
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+            WHEN alu_slt => IF v_op1_s < v_op2_s THEN
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+                                o_res <= X"00000001";
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+                            ELSE
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+                                o_res <= X"00000000";
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+                            END IF;
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+            WHEN alu_xor => o_res <= i_op1 XOR i_op2;
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+            WHEN OTHERS => o_res <= X"00000000";
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+        END CASE;
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+    END PROCESS p_alu;
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+
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+END ARCHITECTURE a_mips_alu;
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+
mips/core.vhd
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+LIBRARY ieee;
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+USE ieee.std_logic_1164.all;
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+USE ieee.numeric_std.all;
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+USE work.mips_types.all;
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+
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+ENTITY e_mips_core IS
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+    PORT (
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+        rst:   IN  std_logic;
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+        clk:   IN  std_logic;
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+        o_res: OUT std_logic_vector(31 DOWNTO 0)
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+    );
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+END ENTITY e_mips_core;
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+
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+ARCHITECTURE a_mips_core OF e_mips_core IS
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+
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+    SIGNAL r_instr: std_logic_vector(31 DOWNTO 0);
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+
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+    SIGNAL s_src_s:  std_logic_vector( 4 DOWNTO 0);
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+    SIGNAL s_src_t:  std_logic_vector( 4 DOWNTO 0);
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+    SIGNAL s_dest:   std_logic_vector( 4 DOWNTO 0);
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+    SIGNAL s_imm_a:  std_logic_vector( 4 DOWNTO 0);
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+    SIGNAL s_imm_16: std_logic_vector(15 DOWNTO 0);
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+    SIGNAL s_imm_26: std_logic_vector(25 DOWNTO 0);
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+    SIGNAL s_op:     t_op;
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+    SIGNAL s_link:   t_link;
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+    SIGNAL s_cmp:    t_cmp;
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+    SIGNAL s_alu:    t_alu;
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+    SIGNAL s_imm:    t_imm;
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+
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+    SIGNAL s_op1: std_logic_vector(31 DOWNTO 0);
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+    SIGNAL s_op2: std_logic_vector(31 DOWNTO 0);
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+
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+    COMPONENT e_mips_decoder IS
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+        PORT (
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+            i_instr:  IN  std_logic_vector(31 DOWNTO 0);
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+            o_src_s:  OUT std_logic_vector( 4 DOWNTO 0);
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+            o_src_t:  OUT std_logic_vector( 4 DOWNTO 0);
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+            o_dest:   OUT std_logic_vector( 4 DOWNTO 0);
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+            o_imm_a:  OUT std_logic_vector( 4 DOWNTO 0);
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+            o_imm_16: OUT std_logic_vector(15 DOWNTO 0);
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+            o_imm_26: OUT std_logic_vector(25 DOWNTO 0);
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+            o_op:     OUT t_op;
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+            o_link:   OUT t_link;
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+            o_cmp:    OUT t_cmp;
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+            o_alu:    OUT t_alu;
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+            o_imm:    OUT t_imm
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+        );
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+    END COMPONENT e_mips_decoder;
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+
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+    COMPONENT e_mips_alu IS
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+        PORT (
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+            i_alu: IN  t_alu;
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+            i_op1: IN  std_logic_vector(31 DOWNTO 0);
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+            i_op2: IN  std_logic_vector(31 DOWNTO 0);
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+            o_res: OUT std_logic_vector(31 DOWNTO 0)
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+        );
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+    END COMPONENT e_mips_alu;
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+
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+BEGIN
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+
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+    decoder: e_mips_decoder
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+        PORT MAP (
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+            i_instr  => r_instr,
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+            o_src_s  => s_src_s,
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+            o_src_t  => s_src_t,
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+            o_dest   => s_dest,
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+            o_imm_a  => s_imm_a,
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+            o_imm_16 => s_imm_16,
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+            o_imm_26 => s_imm_26,
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+            o_op     => s_op,
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+            o_link   => s_link,
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+            o_cmp    => s_cmp,
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+            o_alu    => s_alu,
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+            o_imm    => s_imm
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+        );
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+
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+    s_op1 <= s_src_s & s_src_s & s_src_s & s_src_s & s_src_s & s_src_s & "00";
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+    s_op2 <= s_src_t & s_src_t & s_src_t & s_src_t & s_src_t & s_src_t & "00";
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+
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+    alu: e_mips_alu
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+        PORT MAP (
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+            i_alu => s_alu,
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+            i_op1 => s_op1,
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+            i_op2 => s_op2,
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+            o_res => o_res
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+        );
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+
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+    p_dummy_fetch: PROCESS(rst, clk)
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+    BEGIN
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+        IF rst = '1' THEN
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+            r_instr <= X"00000000";
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+        ELSIF rising_edge(clk) THEN
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+            r_instr <= std_logic_vector(unsigned(r_instr) + to_unsigned(1, 32));
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+        END IF;
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+    END PROCESS p_dummy_fetch;
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+
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+END ARCHITECTURE a_mips_core;
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+
mips/decoder.vhd
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+LIBRARY ieee;
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+USE ieee.std_logic_1164.all;
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+USE ieee.numeric_std.all;
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+USE work.mips_types.all;
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+
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+ENTITY e_mips_decoder IS
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+    PORT (
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+        i_instr:  IN  std_logic_vector(31 DOWNTO 0);
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+        o_src_s:  OUT std_logic_vector( 4 DOWNTO 0);
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+        o_src_t:  OUT std_logic_vector( 4 DOWNTO 0);
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+        o_dest:   OUT std_logic_vector( 4 DOWNTO 0);
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+        o_imm_a:  OUT std_logic_vector( 4 DOWNTO 0);
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+        o_imm_16: OUT std_logic_vector(15 DOWNTO 0);
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+        o_imm_26: OUT std_logic_vector(25 DOWNTO 0);
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+        o_op:     OUT t_op;
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+        o_link:   OUT t_link;
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+        o_cmp:    OUT t_cmp;
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+        o_alu:    OUT t_alu;
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+        o_imm:    OUT t_imm
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+    );
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+END ENTITY e_mips_decoder;
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+
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+ARCHITECTURE a_mips_decoder OF e_mips_decoder IS
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+
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+    TYPE t_enc_type IS (enc_reg, enc_imm, enc_jmp);
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+
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+    SIGNAL s_opcode:   std_logic_vector(5 DOWNTO 0);
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+    SIGNAL s_enc_type: t_enc_type;
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+    SIGNAL s_func:     std_logic_vector(5 DOWNTO 0);
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+
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+BEGIN
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+
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+    s_opcode <= i_instr(31 DOWNTO 26);
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+
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+    p_enc_type: PROCESS(s_opcode)
36 
+    BEGIN
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+        CASE s_opcode IS
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+            WHEN "000000" => s_enc_type <= enc_reg;
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+            WHEN "000010" => s_enc_type <= enc_jmp;
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+            WHEN "011010" => s_enc_type <= enc_jmp;
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+            WHEN OTHERS   => s_enc_type <= enc_imm;
42 
+        END CASE;
43 
+    END PROCESS p_enc_type;
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+
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+    p_src_s: PROCESS(i_instr, s_enc_type)
46 
+    BEGIN
47 
+        CASE s_enc_type IS
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+            WHEN enc_reg => o_src_s <= i_instr(25 DOWNTO 21);
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+            WHEN enc_imm => o_src_s <= i_instr(25 DOWNTO 21);
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+            WHEN OTHERS  => o_src_s <= "00000";
51 
+        END CASE;
52 
+    END PROCESS p_src_s;
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+
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+    p_src_t: PROCESS(i_instr, s_enc_type)
55 
+    BEGIN
56 
+        CASE s_enc_type IS
57 
+            WHEN enc_reg => o_src_t <= i_instr(20 DOWNTO 16);
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+            WHEN enc_imm => o_src_t <= i_instr(20 DOWNTO 16);
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+            WHEN OTHERS  => o_src_t <= "00000";
60 
+        END CASE;
61 
+    END PROCESS p_src_t;
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+
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+    p_dest: PROCESS(i_instr, s_enc_type)
64 
+    BEGIN
65 
+        CASE s_enc_type IS
66 
+            WHEN enc_reg => o_dest <= i_instr(15 DOWNTO 11);
67 
+            WHEN OTHERS  => o_dest <= "00000";
68 
+        END CASE;
69 
+    END PROCESS p_dest;
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+
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+    p_imm_a: PROCESS(i_instr, s_enc_type)
72 
+    BEGIN
73 
+        CASE s_enc_type IS
74 
+            WHEN enc_reg => o_imm_a <= i_instr(10 DOWNTO 6);
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+            WHEN OTHERS  => o_imm_a <= "00000";
76 
+        END CASE;
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+    END PROCESS p_imm_a;
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+
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+    p_func: PROCESS(i_instr, s_enc_type)
80 
+    BEGIN
81 
+        CASE s_enc_type IS
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+            WHEN enc_reg => s_func <= i_instr(5 DOWNTO 0);
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+            WHEN OTHERS  => s_func <= "000000";
84 
+        END CASE;
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+    END PROCESS p_func;
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+
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+    p_imm_16: PROCESS(i_instr, s_enc_type)
88 
+    BEGIN
89 
+        CASE s_enc_type IS
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+            WHEN enc_reg => o_imm_16 <= i_instr(15 DOWNTO 0);
91 
+            WHEN OTHERS  => o_imm_16 <= X"0000";
92 
+        END CASE;
93 
+    END PROCESS p_imm_16;
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+
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+    p_imm_26: PROCESS(i_instr, s_enc_type)
96 
+    BEGIN
97 
+        CASE s_enc_type IS
98 
+            WHEN enc_reg => o_imm_26 <= i_instr(25 DOWNTO 0);
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+            WHEN OTHERS  => o_imm_26 <= X"000000" & "00";
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+        END CASE;
101 
+    END PROCESS p_imm_26;
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+
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+    p_op: PROCESS(s_opcode, s_func)
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+    BEGIN
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+        o_op   <= op_none;
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+        o_link <= link_none;
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+        o_cmp  <= cmp_none;
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+        o_alu  <= alu_none;
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+        o_imm  <= imm_none;
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+        CASE s_opcode IS
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+            WHEN "000000" =>
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+                CASE s_func IS
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+                    WHEN "000000" => o_op <= op_alu; o_alu <= alu_sll; o_imm <= imm_a;
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+                    WHEN "000010" => o_op <= op_alu; o_alu <= alu_srl; o_imm <= imm_a;
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+                    WHEN "000011" => o_op <= op_alu; o_alu <= alu_sra; o_imm <= imm_a;
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+                    WHEN "000100" => o_op <= op_alu; o_alu <= alu_sll;
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+                    WHEN "000110" => o_op <= op_alu; o_alu <= alu_srl;
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+                    WHEN "000111" => o_op <= op_alu; o_alu <= alu_sra;
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+                    WHEN "001000" => o_op <= op_j;
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+                    WHEN "001001" => o_op <= op_j; o_link <= link_link;
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+                    -- TODO: 010xxx, 011xxx missing
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+                    WHEN "100000" => o_op <= op_alu; o_alu <= alu_add;
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+                    WHEN "100001" => o_op <= op_alu; o_alu <= alu_add;
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+                    WHEN "100010" => o_op <= op_alu; o_alu <= alu_sub;
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+                    WHEN "100011" => o_op <= op_alu; o_alu <= alu_sub;
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+                    WHEN "100100" => o_op <= op_alu; o_alu <= alu_and;
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+                    WHEN "100101" => o_op <= op_alu; o_alu <= alu_or;
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+                    WHEN "100110" => o_op <= op_alu; o_alu <= alu_xor;
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+                    WHEN "100111" => o_op <= op_alu; o_alu <= alu_nor;
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+                    WHEN "101010" => o_op <= op_alu; o_alu <= alu_slt;
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+                    WHEN "101011" => o_op <= op_alu; o_alu <= alu_slt;
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+                    WHEN OTHERS => NULL;
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+                END CASE;
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+            WHEN "000010" => o_op <= op_j;
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+            WHEN "000011" => o_op <= op_j; o_link <= link_link; o_imm <= imm_26;
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+            WHEN "000100" => o_op <= op_b; o_cmp <= cmp_eq;
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+            WHEN "000101" => o_op <= op_b; o_cmp <= cmp_ne;
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+            WHEN "000110" => o_op <= op_b; o_cmp <= cmp_lez;
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+            WHEN "000111" => o_op <= op_b; o_cmp <= cmp_gtz;
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+            WHEN "001000" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
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+            WHEN "001001" => o_op <= op_alu; o_alu <= alu_add; o_imm <= imm_16se;
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+            WHEN "001010" => o_op <= op_alu; o_alu <= alu_slt; o_imm <= imm_16se;
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+            WHEN "001011" => o_op <= op_alu; o_alu <= alu_slt; o_imm <= imm_16se;
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+            WHEN "001100" => o_op <= op_alu; o_alu <= alu_and; o_imm <= imm_16ze;
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+            WHEN "001101" => o_op <= op_alu; o_alu <= alu_or; o_imm <= imm_16ze;
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+            WHEN "001110" => o_op <= op_alu; o_alu <= alu_xor; o_imm <= imm_16ze;
147 
+            -- TODO: 011xxx, 100xxx, 101xxx missing
148 
+            WHEN OTHERS => NULL;
149 
+        END CASE;
150 
+    END PROCESS p_op;
151 
+
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+END ARCHITECTURE a_mips_decoder;
153 
+
mips/types.vhd
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+LIBRARY ieee;
2 
+USE ieee.std_logic_1164.all;
3 
+USE ieee.numeric_std.all;
4 
+
5 
+PACKAGE mips_types IS
6 
+
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+    -- operation
8 
+    TYPE t_op IS (
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+        op_none,
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+        op_alu, -- ALU operation
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+        op_b,   -- branch (conditional)
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+        op_j    -- jump
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+    );
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+
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+    -- link (store return address in register)
16 
+    TYPE t_link IS (
17 
+        link_none,
18 
+        link_link  -- link
19 
+    );
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+
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+    -- compare mode
22 
+    TYPE t_cmp IS (
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+        cmp_none,
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+        cmp_eq,   -- equal
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+        cmp_gtz,  -- greater zero
26 
+        cmp_lez,  -- less or equal zero
27 
+        cmp_ne    -- not equal
28 
+    );
29 
+
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+    -- ALU operation
31 
+    TYPE t_alu IS (
32 
+        alu_none,
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+        alu_add,  -- addition
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+        alu_and,  -- bitwise AND
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+        alu_nor,  -- bitwise NOR
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+        alu_or,   -- bitwise OR
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+        alu_sub,  -- subtraction
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+        alu_sll,  -- shift left logically
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+        alu_sra,  -- shift right arithmetically
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+        alu_srl,  -- shift right logically
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+        alu_slt,  -- set on less than
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+        alu_xor   -- bitwise XOR
43 
+    );
44 
+
45 
+    -- immediate usage
46 
+    TYPE t_imm IS (
47 
+        imm_none,
48 
+        imm_a,    -- "a" immediate
49 
+        imm_16se, -- 16 bit immediate, sign-extension
50 
+        imm_16ze, -- 16 bit immediate, zero-extension
51 
+        imm_26    -- 26 bit immediate
52 
+    );
53 
+
54 
+END PACKAGE;
55 
+
mips_sys.xise
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+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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+
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+  <header>
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+    <!-- ISE source project file created by Project Navigator.             -->
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+    <!--                                                                   -->
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+    <!-- This file contains project source information including a list of -->
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+    <!-- project source files, project and process properties.  This file, -->
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+    <!-- along with the project source files, is sufficient to open and    -->
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+    <!-- implement in ISE Project Navigator.                               -->
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+    <!--                                                                   -->
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+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
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+  </header>
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+
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+  <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
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+
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+  <files>
18 
+    <file xil_pn:name="mips/decoder.vhd" xil_pn:type="FILE_VHDL">
19 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
20 
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
21 
+    </file>
22 
+    <file xil_pn:name="mips/types.vhd" xil_pn:type="FILE_VHDL">
23 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
24 
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
25 
+    </file>
26 
+    <file xil_pn:name="mips/alu.vhd" xil_pn:type="FILE_VHDL">
27 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
28 
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
29 
+    </file>
30 
+    <file xil_pn:name="mips/core.vhd" xil_pn:type="FILE_VHDL">
31 
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
32 
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
33 
+    </file>
34 
+    <file xil_pn:name="constraints/clk.ucf" xil_pn:type="FILE_UCF">
35 
+      <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
36 
+    </file>
37 
+    <file xil_pn:name="constraints/rst.ucf" xil_pn:type="FILE_UCF">
38 
+      <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
39 
+    </file>
40 
+  </files>
41 
+
42 
+  <properties>
43 
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
44 
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
45 
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
46 
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
47 
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
48 
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
49 
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
50 
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
51 
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
52 
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
53 
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
54 
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
55 
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
56 
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
57 
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
58 
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
59 
+    <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
60 
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
61 
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
62 
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-4" xil_pn:valueState="default"/>
63 
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-4" xil_pn:valueState="default"/>
64 
+    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
65 
+    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
66 
+    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
67 
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
68 
+    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
69 
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
70 
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
71 
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
72 
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
73 
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
74 
+    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
75 
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
76 
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
77 
+    <property xil_pn:name="Configuration Rate" xil_pn:value="25" xil_pn:valueState="default"/>
78 
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
79 
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
80 
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
81 
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
82 
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
83 
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
84 
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
85 
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
86 
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
87 
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
88 
+    <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
89 
+    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
90 
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
91 
+    <property xil_pn:name="Device" xil_pn:value="xc3s700a" xil_pn:valueState="non-default"/>
92 
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan3A and Spartan3AN" xil_pn:valueState="non-default"/>
93 
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-4" xil_pn:valueState="default"/>
94 
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
95 
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
96 
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence" xil_pn:value="false" xil_pn:valueState="default"/>
97 
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
98 
+    <property xil_pn:name="Dummy Driver for Enable Filter on Suspend Input" xil_pn:value="false" xil_pn:valueState="default"/>
99 
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
100 
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
101 
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
102 
+    <property xil_pn:name="Enable Filter on Suspend Input" xil_pn:value="Please use the ENABLE_SUSPEND implementation constraint." xil_pn:valueState="default"/>
103 
+    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
104 
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
105 
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
106 
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
107 
+    <property xil_pn:name="Enable Power-On Reset Detection" xil_pn:value="true" xil_pn:valueState="default"/>
108 
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset" xil_pn:value="false" xil_pn:valueState="default"/>
109 
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
110 
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="Spartan-3A Starter Kit" xil_pn:valueState="non-default"/>
111 
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
112 
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
113 
+    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
114 
+    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
115 
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
116 
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
117 
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
118 
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
119 
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
120 
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
121 
+    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
122 
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
123 
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
124 
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
125 
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence" xil_pn:value="4" xil_pn:valueState="default"/>
126 
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence" xil_pn:value="5" xil_pn:valueState="default"/>
127 
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
128 
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
129 
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
130 
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
131 
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
132 
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
133 
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
134 
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
135 
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
136 
+    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
137 
+    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
138 
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
139 
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
140 
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
141 
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
142 
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
143 
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
144 
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
145 
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
146 
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
147 
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
148 
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
149 
+    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
150 
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
151 
+    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
152 
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
153 
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
154 
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
155 
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
156 
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|e_mips_core|a_mips_core" xil_pn:valueState="non-default"/>
157 
+    <property xil_pn:name="Implementation Top File" xil_pn:value="mips/core.vhd" xil_pn:valueState="non-default"/>
158 
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/e_mips_core" xil_pn:valueState="non-default"/>
159 
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
160 
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
161 
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
162 
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
163 
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
164 
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
165 
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
166 
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
167 
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
168 
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
169 
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
170 
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
171 
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
172 
+    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
173 
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
174 
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
175 
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
176 
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
177 
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
178 
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
179 
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
180 
+    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
181 
+    <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
182 
+    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
183 
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
184 
+    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
185 
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
186 
+    <property xil_pn:name="Max Fanout" xil_pn:value="500" xil_pn:valueState="default"/>
187 
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
188 
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
189 
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
190 
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
191 
+    <property xil_pn:name="MultiBoot: Next Configuration Mode" xil_pn:value="001" xil_pn:valueState="default"/>
192 
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
193 
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration" xil_pn:value="true" xil_pn:valueState="default"/>
194 
+    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
195 
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
196 
+    <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
197 
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
198 
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
199 
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
200 
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
201 
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
202 
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
203 
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
204 
+    <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
205 
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
206 
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
207 
+    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
208 
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
209 
+    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
210 
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
211 
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
212 
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
213 
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
214 
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
215 
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
216 
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
217 
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
218 
+    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
219 
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
220 
+    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
221 
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
222 
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
223 
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
224 
+    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
225 
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
226 
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
227 
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
228 
+    <property xil_pn:name="Output File Name" xil_pn:value="e_mips_core" xil_pn:valueState="default"/>
229 
+    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
230 
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
231 
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
232 
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
233 
+    <property xil_pn:name="Package" xil_pn:value="fg484" xil_pn:valueState="non-default"/>
234 
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
235 
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
236 
+    <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
237 
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
238 
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
239 
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream" xil_pn:value="false" xil_pn:valueState="default"/>
240 
+    <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
241 
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
242 
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="e_mips_core_map.vhd" xil_pn:valueState="default"/>
243 
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="e_mips_core_timesim.vhd" xil_pn:valueState="default"/>
244 
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="e_mips_core_synthesis.vhd" xil_pn:valueState="default"/>
245 
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="e_mips_core_translate.vhd" xil_pn:valueState="default"/>
246 
+    <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
247 
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
248 
+    <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
249 
+    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
250 
+    <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
251 
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
252 
+    <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
253 
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
254 
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
255 
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
256 
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
257 
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
258 
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
259 
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
260 
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
261 
+    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
262 
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
263 
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
264 
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
265 
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
266 
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="e_mips_core" xil_pn:valueState="default"/>
267 
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
268 
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
269 
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
270 
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
271 
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
272 
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
273 
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
274 
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
275 
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
276 
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
277 
+    <property xil_pn:name="Resource Sharing" xil_pn:value="false" xil_pn:valueState="non-default"/>
278 
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
279 
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs" xil_pn:value="false" xil_pn:valueState="default"/>
280 
+    <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
281 
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
282 
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
283 
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
284 
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
285 
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
286 
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
287 
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
288 
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
289 
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
290 
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
291 
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
292 
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
293 
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
294 
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
295 
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
296 
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
297 
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
298 
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
299 
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
300 
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
301 
+    <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
302 
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
303 
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
304 
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
305 
+    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
306 
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
307 
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
308 
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
309 
+    <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/>
310 
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
311 
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
312 
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
313 
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
314 
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
315 
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
316 
+    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
317 
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
318 
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
319 
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
320 
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
321 
+    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
322 
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
323 
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
324 
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
325 
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
326 
+    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
327 
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
328 
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
329 
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
330 
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
331 
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
332 
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
333 
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
334 
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
335 
+    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
336 
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
337 
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
338 
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
339 
+    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
340 
+    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
341 
+    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
342 
+    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
343 
+    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
344 
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
345 
+    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
346 
+    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
347 
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
348 
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
349 
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
350 
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
351 
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
352 
+    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
353 
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
354 
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
355 
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
356 
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
357 
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
358 
+    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
359 
+    <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
360 
+    <property xil_pn:name="Wakeup Clock" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
361 
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
362 
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
363 
+    <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
364 
+    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
365 
+    <!--                                                                                  -->
366 
+    <!-- The following properties are for internal use only. These should not be modified.-->
367 
+    <!--                                                                                  -->
368 
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
369 
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="mips_sys" xil_pn:valueState="non-default"/>
370 
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3a" xil_pn:valueState="default"/>
371 
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
372 
+    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
373 
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
374 
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
375 
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
376 
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
377 
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
378 
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-01-23T20:57:37" xil_pn:valueState="non-default"/>
379 
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="504447C81FC3113F3078F816935626AA" xil_pn:valueState="non-default"/>
380 
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
381 
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
382 
+  </properties>
383 
+
384 
+  <bindings>
385 
+    <binding xil_pn:location="/e_mips_core" xil_pn:name="constraints/clk.ucf"/>
386 
+    <binding xil_pn:location="/e_mips_core" xil_pn:name="constraints/rst.ucf"/>
387 
+  </bindings>
388 
+
389 
+  <libraries/>
390 
+
391 
+  <autoManagedFiles>
392 
+    <!-- The following files are identified by `include statements in verilog -->
393 
+    <!-- source files and are automatically managed by Project Navigator.     -->
394 
+    <!--                                                                      -->
395 
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
396 
+    <!-- project is analyzed based on files automatically identified as       -->
397 
+    <!-- include files.                                                       -->
398 
+  </autoManagedFiles>
399 
+
400 
+</project>
0 401