MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
updated project files
2963923 @ 2012-03-16 21:34:51
| blocks | improve synchonous FIFO implementation (get rid of delays between reads) | 2012-03-11 18:59:11 |
|---|---|---|
| constraints | adapt ethernet TX clock timing constraint to transmission of data on falling edge | 2012-03-07 21:18:54 |
| doc | MIPS ISA spec | 2012-01-24 21:41:27 |
| fw | enable optimization for size | 2012-03-15 21:45:23 |
| io | made MAC configurable in ethernet peripheral | 2012-03-11 20:48:30 |
| mips | fixed decoding of M[FT]{HI|LO} | 2012-03-13 21:11:43 |
| stuff | implemented ethernet RX busmaster -> packet reception working | 2012-03-03 23:42:55 |
| system | implemented ethernet TX frame generation and register interface (no firmware yet, no simulation testbed support yet, not tested yet) | 2012-03-05 22:01:56 |
| test | implemented ethernet RX packet and TX clock in testbed | 2012-03-06 20:48:33 |
| .gitignore | impact project | 2012-02-11 00:32:06 |
| Default.wcfg | updated project files | 2012-03-16 21:34:51 |
| mips_sys.ipf | impact project | 2012-02-11 00:32:06 |
| mips_sys.xise | made MAC configurable in ethernet peripheral | 2012-03-11 20:48:30 |