MIPS I system running on Xilinx Spartan-3A FPGA Starter Kit: VHDL code for processor core very similar to MIPS I and for several peripherals, C firmware to run on this system
Stefan Schuermans
implented basic system with core, instr memory, data memory
b5b070d @ 2012-02-06 21:28:00
| .. | ||
|---|---|---|
| alu.vhd | added decoding of simple load/store instructions and lui instruction implemented lui instruction fix syntax bug in regs | 2012-01-26 20:50:15 |
| cmp.vhd | compare unit, initial PC ideas | 2012-01-25 18:56:29 |
| core.vhd | implemented ... and link -> MIPSel1 core complete | 2012-02-05 21:16:11 |
| decoder.vhd | decoding MULT(U)/DIV(U) -> MIPSel1 decoder complete | 2012-02-05 17:32:53 |
| div.vhd | implemented divider | 2012-02-05 20:59:58 |
| mul_fast.vhd | second version of multiplier (slower, i.e. more stages -> faster clock) | 2012-02-05 21:39:45 |
| mul_slow.vhd | second version of multiplier (slower, i.e. more stages -> faster clock) | 2012-02-05 21:39:45 |
| regs.vhd | fix sensitivity lists | 2012-02-05 13:21:46 |
| shifter.vhd | fix unused signals | 2012-02-05 13:21:27 |
| types.vhd | decoding MULT(U)/DIV(U) -> MIPSel1 decoder complete | 2012-02-05 17:32:53 |