mips_sys

@@ -76,6 +76,10 @@ ARCHITECTURE a_mips_core OF e_mips_core IS

     SIGNAL s_reg_wr_hi_lo_data: std_logic_vector(31 DOWNTO 0);

     SIGNAL s_reg_wr_hi_lo_en:   std_logic;

+    SIGNAL s_reg_wr_link_no:   std_logic_vector( 4 DOWNTO 0);

+    SIGNAL s_reg_wr_link_data: std_logic_vector(31 DOWNTO 0);

+    SIGNAL s_reg_wr_link_en:   std_logic;

+

     SIGNAL s_reg_wr_no:   std_logic_vector( 4 DOWNTO 0);

     SIGNAL s_reg_wr_data: std_logic_vector(31 DOWNTO 0);

     SIGNAL s_reg_wr_en:   std_logic;

@@ -361,7 +365,8 @@ BEGIN

     p_reg_wr: PROCESS(s_stall,

                       s_reg_wr_alu_no, s_reg_wr_alu_data, s_reg_wr_alu_en,

                       s_reg_wr_data_no, s_reg_wr_data_data, s_reg_wr_data_en,

-                      s_reg_wr_hi_lo_no, s_reg_wr_hi_lo_data, s_reg_wr_hi_lo_en)

+                      s_reg_wr_hi_lo_no, s_reg_wr_hi_lo_data, s_reg_wr_hi_lo_en,

+                      s_reg_wr_link_no, s_reg_wr_link_data, s_reg_wr_link_en)

     BEGIN

         s_reg_wr_no   <= (OTHERS => '0');

         s_reg_wr_data <= (OTHERS => '0');

@@ -379,6 +384,10 @@ BEGIN

                 s_reg_wr_no   <= s_reg_wr_hi_lo_no;

                 s_reg_wr_data <= s_reg_wr_hi_lo_data;

                 s_reg_wr_en   <= '1';

+            ELSIF s_reg_wr_link_en = '1' THEN

+                s_reg_wr_no   <= s_reg_wr_link_no;

+                s_reg_wr_data <= s_reg_wr_link_data;

+                s_reg_wr_en   <= '1';

             END IF;

         END IF;

     END PROCESS p_reg_wr;

@@ -617,4 +626,15 @@ BEGIN

     s_div_signed <= '1' WHEN r_op = op_div ELSE '0';

     s_div_start  <= '1' WHEN i_stall = '0' AND (r_op = op_div OR r_op = op_divu) ELSE '0';

+    p_link: PROCESS(r_pc, r_link)

+    BEGIN

+        s_reg_wr_link_no   <= std_logic_vector(to_unsigned(31, 5));

+        s_reg_wr_link_data <= std_logic_vector(signed(r_pc) + to_signed(4, 32));

+        IF r_link = link_link THEN

+            s_reg_wr_link_en <= '1';

+        ELSE

+            s_reg_wr_link_en <= '0';

+        END IF;

+    END PROCESS p_link;

+

 END ARCHITECTURE a_mips_core;