added decoding of simple load/store instructions and lui instruction implemented lui instruction fix syntax bug in regs (ee62a05) - mips_sys · BlinkenArea

added decoding of simple load/store instructions and lui instruction implemented lui instruction fix syntax bug in regs

Stefan Schuermans commited on 2012-01-26 20:50:15
Showing 5 changed files, with 39 additions and 8 deletions.

mips/alu.vhd 5d7c5da..8fe9517
mips/core.vhd 15b81be..8d8642e
mips/decoder.vhd 43e0896..48e408b
mips/regs.vhd 2d72248..03faacd
mips/types.vhd da3b002..cf16e6a

mips/alu.vhd

@@ -70,6 +70,7 @@ BEGIN
                              ELSE
                                  o_res <= X"00000000";
                              END IF;
+            WHEN alu_up => o_res <= i_op2(15 DOWNTO 0) & X"0000";
             WHEN alu_xor => o_res <= i_op1 XOR i_op2;
             WHEN OTHERS => o_res <= X"00000000";
         END CASE;

mips/core.vhd

View file @ ee62a05

@@ -30,6 +30,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
     SIGNAL n_cmp:    t_cmp;
     SIGNAL n_alu:    t_alu;
     SIGNAL n_imm:    t_imm;
+    SIGNAL n_ldst:   t_ldst;
 
     SIGNAL r_reg_s:  std_logic_vector( 4 DOWNTO 0);
     SIGNAL r_reg_t:  std_logic_vector( 4 DOWNTO 0);
@@ -42,6 +43,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
     SIGNAL r_cmp:    t_cmp;
     SIGNAL r_alu:    t_alu;
     SIGNAL r_imm:    t_imm;
+    SIGNAL r_ldst:   t_ldst;
 
     SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
     SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
@@ -71,7 +73,8 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
             o_link:   OUT t_link;
             o_cmp:    OUT t_cmp;
             o_alu:    OUT t_alu;
-            o_imm:    OUT t_imm
+            o_imm:    OUT t_imm;
+            o_ldst:   OUT t_ldst
         );
     END COMPONENT e_mips_decoder;
 
@@ -122,7 +125,8 @@ BEGIN
             o_link   => n_link,
             o_cmp    => n_cmp,
             o_alu    => n_alu,
-            o_imm    => n_imm
+            o_imm    => n_imm,
+            o_ldst   => n_ldst
         );
 
     regs: e_mips_regs
@@ -183,6 +187,7 @@ BEGIN
             r_cmp    <= cmp_none;
             r_alu    <= alu_none;
             r_imm    <= imm_none;
+            r_ldst   <= ldst_none;
         ELSIF rising_edge(clk) THEN
             r_reg_s  <= n_reg_s;
             r_reg_t  <= n_reg_t;
@@ -195,6 +200,7 @@ BEGIN
             r_cmp    <= n_cmp;
             r_alu    <= n_alu;
             r_imm    <= n_imm;
+            r_ldst   <= n_ldst;
         END IF;
     END PROCESS p_dec2ex;
 
@@ -234,7 +240,7 @@ BEGIN
         END IF;
     END PROCESS p_cmp_in;
 
-    p_reg_wr: PROCESS(r_op, r_imm, r_reg_t, r_reg_d)
+    p_reg_wr: PROCESS(r_op, r_imm, r_reg_t, r_reg_d, s_alu_res)
     BEGIN
         s_reg_wr_no   <= (OTHERS => '0');
         s_reg_wr_data <= (OTHERS => '0');

mips/decoder.vhd

View file @ ee62a05

@@ -16,7 +16,8 @@ ENTITY e_mips_decoder IS
         o_link:   OUT t_link;
         o_cmp:    OUT t_cmp;
         o_alu:    OUT t_alu;
-        o_imm:    OUT t_imm
+        o_imm:    OUT t_imm;
+        o_ldst:   OUT t_ldst
     );
 END ENTITY e_mips_decoder;
 
@@ -102,6 +103,7 @@ BEGIN
         o_cmp  <= cmp_none;
         o_alu  <= alu_none;
         o_imm  <= imm_none;
+        o_ldst <= ldst_none;
         CASE s_opcode IS
             WHEN "000000" =>
                 CASE s_func IS
@@ -146,7 +148,16 @@ BEGIN
             WHEN "001100" => o_op <= op_alu; o_alu <= alu_and; o_imm <= imm_16ze;
             WHEN "001101" => o_op <= op_alu; o_alu <= alu_or; o_imm <= imm_16ze;
             WHEN "001110" => o_op <= op_alu; o_alu <= alu_xor; o_imm <= imm_16ze;
-            -- TODO: 011xxx, 100xxx, 101xxx missing
+            WHEN "001111" => o_op <= op_alu; o_alu <= alu_up; o_imm <= imm_16ze;
+            -- TODO: 011xxx missing
+            WHEN "100000" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_b;
+            WHEN "100001" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_h;
+            WHEN "100011" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_w;
+            WHEN "100100" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_bu;
+            WHEN "100101" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_hu;
+            WHEN "101000" => o_op <= op_s; o_imm <= imm_16se; o_ldst <= ldst_b;
+            WHEN "101001" => o_op <= op_s; o_imm <= imm_16se; o_ldst <= ldst_h;
+            WHEN "101011" => o_op <= op_s; o_imm <= imm_16se; o_ldst <= ldst_w;
             WHEN OTHERS => NULL;
         END CASE;
     END PROCESS p_op;

mips/regs.vhd

View file @ ee62a05

@@ -39,9 +39,9 @@ BEGIN
     p_write: PROCESS(rst, clk)
     BEGIN
         IF rst = '1' THEN
-            r_regs <= (OTHERS => '0');
+            r_regs <= (OTHERS => X"00000000");
         ELSIF rising_edge(clk) THEN
-            IF i_wr_en = '1' AND i_wr_no /= (OTHERS => '0') THEN
+            IF i_wr_en = '1' AND i_wr_no /= "00000" THEN
                 r_regs(no2idx(i_wr_no)) <= i_wr_data;
             END IF;
         END IF;

mips/types.vhd

View file @ ee62a05

@@ -8,7 +8,9 @@ PACKAGE mips_types IS
     TYPE t_op IS (
         op_none,
         op_alu, -- ALU operation
-        op_j    -- jump or branch
+        op_j,   -- jump or branch
+        op_l,   -- load
+        op_s    -- store
     );
 
     -- link (store return address in register)
@@ -41,6 +43,7 @@ PACKAGE mips_types IS
         alu_srl,  -- shift right logically
         alu_slt,  -- set on less than
         alu_sltu, -- set on less than unsigned
+        alu_up,   -- move to upper half
         alu_xor   -- bitwise XOR
     );
 
@@ -53,5 +56,15 @@ PACKAGE mips_types IS
         imm_26    -- 26 bit immediate
     );
 
+    -- load/store type
+    TYPE t_ldst IS (
+        ldst_none,
+        ldst_b,    -- byte (sign-extension)
+        ldst_bu,   -- byte unsigned (zero-extension)
+        ldst_h,    -- half word (16 bit) (sign-extension)
+        ldst_hu,   -- half word unsigned (16 bit) (zero-extension)
+        ldst_w     -- word (32 bit)
+    );
+
 END PACKAGE;
 


...	...	@@ -70,6 +70,7 @@ BEGIN
70	70	ELSE
71	71	o_res <= X"00000000";
72	72	END IF;
	73	+ WHEN alu_up => o_res <= i_op2(15 DOWNTO 0) & X"0000";
73	74	WHEN alu_xor => o_res <= i_op1 XOR i_op2;
74	75	WHEN OTHERS => o_res <= X"00000000";
75	76	END CASE;

...	...	@@ -30,6 +30,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
30	30	SIGNAL n_cmp: t_cmp;
31	31	SIGNAL n_alu: t_alu;
32	32	SIGNAL n_imm: t_imm;
	33	+ SIGNAL n_ldst: t_ldst;
33	34
34	35	SIGNAL r_reg_s: std_logic_vector( 4 DOWNTO 0);
35	36	SIGNAL r_reg_t: std_logic_vector( 4 DOWNTO 0);
...	...	@@ -42,6 +43,7 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
42	43	SIGNAL r_cmp: t_cmp;
43	44	SIGNAL r_alu: t_alu;
44	45	SIGNAL r_imm: t_imm;
	46	+ SIGNAL r_ldst: t_ldst;
45	47
46	48	SIGNAL s_val_s: std_logic_vector(31 DOWNTO 0);
47	49	SIGNAL s_val_t: std_logic_vector(31 DOWNTO 0);
...	...	@@ -71,7 +73,8 @@ ARCHITECTURE a_mips_core OF e_mips_core IS
71	73	o_link: OUT t_link;
72	74	o_cmp: OUT t_cmp;
73	75	o_alu: OUT t_alu;
74		- o_imm: OUT t_imm
	76	+ o_imm: OUT t_imm;
	77	+ o_ldst: OUT t_ldst
75	78	);
76	79	END COMPONENT e_mips_decoder;
77	80
...	...	@@ -122,7 +125,8 @@ BEGIN
122	125	o_link => n_link,
123	126	o_cmp => n_cmp,
124	127	o_alu => n_alu,
125		- o_imm => n_imm
	128	+ o_imm => n_imm,
	129	+ o_ldst => n_ldst
126	130	);
127	131
128	132	regs: e_mips_regs
...	...	@@ -183,6 +187,7 @@ BEGIN
183	187	r_cmp <= cmp_none;
184	188	r_alu <= alu_none;
185	189	r_imm <= imm_none;
	190	+ r_ldst <= ldst_none;
186	191	ELSIF rising_edge(clk) THEN
187	192	r_reg_s <= n_reg_s;
188	193	r_reg_t <= n_reg_t;
...	...	@@ -195,6 +200,7 @@ BEGIN
195	200	r_cmp <= n_cmp;
196	201	r_alu <= n_alu;
197	202	r_imm <= n_imm;
	203	+ r_ldst <= n_ldst;
198	204	END IF;
199	205	END PROCESS p_dec2ex;
200	206
...	...	@@ -234,7 +240,7 @@ BEGIN
234	240	END IF;
235	241	END PROCESS p_cmp_in;
236	242
237		- p_reg_wr: PROCESS(r_op, r_imm, r_reg_t, r_reg_d)
	243	+ p_reg_wr: PROCESS(r_op, r_imm, r_reg_t, r_reg_d, s_alu_res)
238	244	BEGIN
239	245	s_reg_wr_no <= (OTHERS => '0');
240	246	s_reg_wr_data <= (OTHERS => '0');

...	...	@@ -16,7 +16,8 @@ ENTITY e_mips_decoder IS
16	16	o_link: OUT t_link;
17	17	o_cmp: OUT t_cmp;
18	18	o_alu: OUT t_alu;
19		- o_imm: OUT t_imm
	19	+ o_imm: OUT t_imm;
	20	+ o_ldst: OUT t_ldst
20	21	);
21	22	END ENTITY e_mips_decoder;
22	23
...	...	@@ -102,6 +103,7 @@ BEGIN
102	103	o_cmp <= cmp_none;
103	104	o_alu <= alu_none;
104	105	o_imm <= imm_none;
	106	+ o_ldst <= ldst_none;
105	107	CASE s_opcode IS
106	108	WHEN "000000" =>
107	109	CASE s_func IS
...	...	@@ -146,7 +148,16 @@ BEGIN
146	148	WHEN "001100" => o_op <= op_alu; o_alu <= alu_and; o_imm <= imm_16ze;
147	149	WHEN "001101" => o_op <= op_alu; o_alu <= alu_or; o_imm <= imm_16ze;
148	150	WHEN "001110" => o_op <= op_alu; o_alu <= alu_xor; o_imm <= imm_16ze;
149		- -- TODO: 011xxx, 100xxx, 101xxx missing
	151	+ WHEN "001111" => o_op <= op_alu; o_alu <= alu_up; o_imm <= imm_16ze;
	152	+ -- TODO: 011xxx missing
	153	+ WHEN "100000" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_b;
	154	+ WHEN "100001" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_h;
	155	+ WHEN "100011" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_w;
	156	+ WHEN "100100" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_bu;
	157	+ WHEN "100101" => o_op <= op_l; o_imm <= imm_16se; o_ldst <= ldst_hu;
	158	+ WHEN "101000" => o_op <= op_s; o_imm <= imm_16se; o_ldst <= ldst_b;
	159	+ WHEN "101001" => o_op <= op_s; o_imm <= imm_16se; o_ldst <= ldst_h;
	160	+ WHEN "101011" => o_op <= op_s; o_imm <= imm_16se; o_ldst <= ldst_w;
150	161	WHEN OTHERS => NULL;
151	162	END CASE;
152	163	END PROCESS p_op;

...	...	@@ -39,9 +39,9 @@ BEGIN
39	39	p_write: PROCESS(rst, clk)
40	40	BEGIN
41	41	IF rst = '1' THEN
42		- r_regs <= (OTHERS => '0');
	42	+ r_regs <= (OTHERS => X"00000000");
43	43	ELSIF rising_edge(clk) THEN
44		- IF i_wr_en = '1' AND i_wr_no /= (OTHERS => '0') THEN
	44	+ IF i_wr_en = '1' AND i_wr_no /= "00000" THEN
45	45	r_regs(no2idx(i_wr_no)) <= i_wr_data;
46	46	END IF;
47	47	END IF;

...	...	@@ -8,7 +8,9 @@ PACKAGE mips_types IS
8	8	TYPE t_op IS (
9	9	op_none,
10	10	op_alu, -- ALU operation
11		- op_j -- jump or branch
	11	+ op_j, -- jump or branch
	12	+ op_l, -- load
	13	+ op_s -- store
12	14	);
13	15
14	16	-- link (store return address in register)
...	...	@@ -41,6 +43,7 @@ PACKAGE mips_types IS
41	43	alu_srl, -- shift right logically
42	44	alu_slt, -- set on less than
43	45	alu_sltu, -- set on less than unsigned
	46	+ alu_up, -- move to upper half
44	47	alu_xor -- bitwise XOR
45	48	);
46	49
...	...	@@ -53,5 +56,15 @@ PACKAGE mips_types IS
53	56	imm_26 -- 26 bit immediate
54	57	);
55	58
	59	+ -- load/store type
	60	+ TYPE t_ldst IS (
	61	+ ldst_none,
	62	+ ldst_b, -- byte (sign-extension)
	63	+ ldst_bu, -- byte unsigned (zero-extension)
	64	+ ldst_h, -- half word (16 bit) (sign-extension)
	65	+ ldst_hu, -- half word unsigned (16 bit) (zero-extension)
	66	+ ldst_w -- word (32 bit)
	67	+ );
	68	+
56	69	END PACKAGE;
57	70
58	71